Post B6nM06BQGBFpTzXCtM by azonenberg@ioc.exchange
 (DIR) More posts by azonenberg@ioc.exchange
 (DIR) Post #B6mXt6MCDi7WHp2mNk by azonenberg@ioc.exchange
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       Playing with the Efinix Ti375 SERDES
       
 (DIR) Post #B6mYmqkpPxJo719Faa by azonenberg@ioc.exchange
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       So far I haven't managed to get it to pass the SFF-8431 host eye mask with any equalizer settings I've tested (after de-embedding the SFP+ host compliance test fixture and the cable, so should be at the SFP+ connector mating plane).It's close, but there's a touch of overshoot I'm trying to eliminate plus there's a little too much jitter in the horizontal axis so I'm getting ~1.7e-4 mask hit rate
       
 (DIR) Post #B6maTYkcKUaAgKykZk by azonenberg@ioc.exchange
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       Huh, I'm actually getting better jitter performance with just a direct measurement and no de-embeds.I wonder if the S-params I'm using aren't as good as I thought they were
       
 (DIR) Post #B6mb9C8ylweejJE9Ng by azonenberg@ioc.exchange
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       Yeah it looks like the de-embed opens the eye up by 30+ mV in the vertical axis but adds ~3ps of jitter which is just enough to push it over the edge into failing the mask test
       
 (DIR) Post #B6mbU9fr9LnR9RbFTM by azonenberg@ioc.exchange
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       Tweaked the equalizer slightly and now it's passing the mask with no de-embed through the breakout fixture and cables
       
 (DIR) Post #B6mcJLHpjaW1w4lsgq by ldcd@social.treehouse.systems
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       @azonenberg how's the config for the IP, is there a DRP style port or just a sea of wires/parameters
       
 (DIR) Post #B6mcJLTX25sCWMFDvM by azonenberg@ioc.exchange
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       @ldcd There is a DRP and it's standard AMBA APB although I haven't tried using it yet. Only configured through the GUI to date (the transceivers are not yet supported for RTL primitive instantiation although I am pushing them to add that in the future)
       
 (DIR) Post #B6mcRPu4SAC2ZSVThw by azonenberg@ioc.exchange
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       @ldcd The hard PCIe IP is from Cadence so I'm guessing this is probably like a Cadence PCIe gen4/5 PHY IP that they have some custom mux logic hooked up to so you can either wire up the PIPE interface to the PCIe hard block, or the raw SERDES to your gateware
       
 (DIR) Post #B6mcf6VdMC6gTWbRzM by jakob@mastodon.chaosfield.at
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       @azonenberg how are you measuring the S parameters of such a fixture? Not that I think that I could help in any way - just interested on how you'd do that as I don't think SFP cal-kits exist?
       
 (DIR) Post #B6md038V5qRg5wlomG by ldcd@social.treehouse.systems
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       @azonenberg oh it shares the transciever, yeah that would make sense then
       
 (DIR) Post #B6md03LcJ4wAkcuIDo by azonenberg@ioc.exchange
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       @ldcd yes there are four quads, two of which have a hard PCIe block available (but you don't have to use it, you can also use it as a naked transceiver) and the other two are only usable as SERDES to FPGA fabric.The PCIe block supports up to gen4 x4 speed (so 16 GT/s PHY operation) but it appears that "PMA Direct" mode (i.e. transceiver to FPGA fabric) tops out at 12.5 Gbps - maybe there's a critical timing path somewhere that made it not work at 16, or they just never tested faster?Future Titanium parts will apparently support 25 Gbps SERDES operation, according to my sales rep it's the same IP block and the big issue preventing the current gen ones from going faster is actually SI on the substrate
       
 (DIR) Post #B6md7PGlCW02lc8qxc by azonenberg@ioc.exchange
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       @ldcd At some point I will try using the pcie ip to talk to a stm32mp2 but I have other things to play with first.Like the hard quad core VexRISCV that is apparently able to clock up to 1 GHz
       
 (DIR) Post #B6mdnOhLiMvR9rbLI8 by ldcd@social.treehouse.systems
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       @azonenberg oh it's Vex?
       
 (DIR) Post #B6mdnOsL3ViRhwk7Q8 by azonenberg@ioc.exchange
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       @ldcd https://www.efinixinc.com/products-riscv.html#pills-hardened
       
 (DIR) Post #B6nM06BQGBFpTzXCtM by azonenberg@ioc.exchange
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       @jakob I didn't, the data came from the manufacturer. I don't know how they characterized it.
       
 (DIR) Post #B6nMBwwGSMqyHp5yoC by jakob@mastodon.chaosfield.at
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       @azonenberg ah ok