Post B6jUrBcGoSB0gL4siG by azonenberg@ioc.exchange
 (DIR) More posts by azonenberg@ioc.exchange
 (DIR) Post #B6jURqp2zFw6x1yP1E by azonenberg@ioc.exchange
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       It's here! Just need to find time to play with it...
       
 (DIR) Post #B6jUrBcGoSB0gL4siG by azonenberg@ioc.exchange
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       First step will obviously be a blinky or something, then probably getting a PRBS out the SFP+ interface to my big scope, then try to port my 10GbE MAC/PCS to it.
       
 (DIR) Post #B6jW6qF29RZuycEoU4 by roukemap@social.treehouse.systems
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       @azonenberg does it include a heatsink or is it low enough power not to need one when maxxed out?
       
 (DIR) Post #B6jW6qS9Mg4PdINHvc by azonenberg@ioc.exchange
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       @roukemap There is one but for some reason it doesn't ship installed.I plan to get some nice macro photos of the package markings, speed grade, date code, etc before installing it
       
 (DIR) Post #B6jXQUPL8dZf0RzWKW by dianea@lgbtqia.space
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       @azonenberg 362880 cells and 1344 DSPs 😁 with high speed everything everywhere!
       
 (DIR) Post #B6jXQUkxqEs65W6n2G by azonenberg@ioc.exchange
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       @dianea And a hard RISC-V processor, that is just hanging off the side of the FPGA as a peripheral and doesn't control anything unless you ask it to (glares at Zynq/Versal). You don't even have to use it.And a ton of SERDES all over the place. The bigger Titanium parts are supposed to go up to 40x 25G SERDES although those aren't available yet. Still plenty of fun to be had with the Ti375 though.The big thing I want to do is feel out the tooling maturity and get a sense of their python API that they use instead of tcl for a lot of stuff. And see if this is something I might be willing to risk integrating with a "real" design in the future.Also see about maybe fabricating some adapters to go from the PCIe AIC to the mini PCIe on the STM32MP257F-EV1 to get the MP2 to talk PCIe to it.Quad 1 GHz VexRiscV is nice, but it's probably not going to be competitive with a dual 1.5 GHz A35 for most purposes.(And more importantly the STM32MP2 has a lot of extra GPIOs I can use for other stuff without burning expensive FPGA pins, and hard AES accelerator and TRNG which are lacking in the Titanium)
       
 (DIR) Post #B6jXXn9jpZG7BFAxP6 by azonenberg@ioc.exchange
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       @dianea I would love to gang a couple of big Titanium parts down the road and make a 40/100G switch to replace the FS switches I'm using today. This had been on the menu for a long time but large Kintex U+ parts weren't supported by the free toolchain so I wasn't thrilled about the idea.
       
 (DIR) Post #B6jXrBYnJxVcN28wL2 by azonenberg@ioc.exchange
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       @dianea but like with 40x 25G SERDES I could do ten ports of 40/100G as a self contained switch.Or I could do say eight edge-facing front panel ports plus a 2x 100G ring bus to adjacent line cards or something. Would need to think about how many serdes i wanted to use for internal vs external stuff
       
 (DIR) Post #B6jY39auSK5HkSq6eO by azonenberg@ioc.exchange
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       @dianea And the Ti375 has 16 transceivers so i could make it a drop-in replacement for the ku5p on my first generation LATENTRED switch board in the future, and make a MP2 + Titanium based logic board that would fit the existing chassis and line cards.The uplinks would drop from 25G to 10G though, so I would probably hold off on that until the Ti450 or something was out with 25G transceivers
       
 (DIR) Post #B6jZMPef4EZp11LEwq by dianea@lgbtqia.space
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       @azonenberg  RISC-V and FPGA is enough power to control the universe 🫠
       
 (DIR) Post #B6jZMPuy5bcXpayGMi by azonenberg@ioc.exchange
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       @dianea I still want hardware AES and TRNG because I do not trust gateware RNGs to be good enough for cryptographic purposes, the toolchain is going to go out of its way to make it deterministic and it's very easy to have things optimized in a way that breaks it
       
 (DIR) Post #B6jZNhqotrpxjte50S by azonenberg@ioc.exchange
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       @dianea and you can have things like injection locking of ring oscillators through the PDN if you are not extremely careful
       
 (DIR) Post #B6jnomcQgDU3hgigiG by funkylab@mastodon.social
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       @azonenberg I'd really be curious how well the quadcore RISC-V lends itself to high speed data shuffling