Post B6E3seoIYYoFUOfkrw by azonenberg@ioc.exchange
 (DIR) More posts by azonenberg@ioc.exchange
 (DIR) Post #B6E2QpikIYMjGUFBXk by azonenberg@ioc.exchange
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       @pcy @leo @gsuberland A normal fanout buffer is just a buffer that replicates the input clock at the output(s), inherently introducing some phase shift.A zero delay buffer is a possible configuration for a PLL based synthesizer that adjusts its local oscillator so the output clock is exactly aligned to the input. Not something you need for PCIe since the refclk is just there for the SERDES to use as a frequency reference, phase doesn't matter at all
       
 (DIR) Post #B6E3seoIYYoFUOfkrw by azonenberg@ioc.exchange
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       @pcy @leo @gsuberland Generally this is just a possible mode of operation for a more complex synthesizer that also lets you output phase shifted clocks, multiples or divisions of an input frequency, etc.As far as PCIe routing really the main important part is to maintain the specified impedance, I think 85 ohms differential, as much as possible while minimizing discontinuities at connectors etc. And staying within the overall loss budget but that shouldn't be too hard.
       
 (DIR) Post #B6EDC1sbuLD47z09xY by gsuberland@chaos.social
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       @azonenberg @pcy @leo yup.on that note, PCIe 4.0 is fast enough to where you actually have to pay some proper attention to your link loss budget, especially if you want it to work in a bottom slot where the motherboard already ate half your loss budget by the time the lanes hit the connector. so pay attention to your stackup / impedance matching, and make sure to check out the routing guidance appnotes for whichever downstream connectors you're using on the carrier.
       
 (DIR) Post #B6EZ5BkV0vc7hWLoQq by leo@60228.dev
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       @azonenberg @pcy @gsuberland thanks, that's mostly what i gathered, was just slightly unclear on the intended application for things like renesas's 9DBL0452 but i guess people might be buying them for things other than pcie too even if that's what it's advertised for?