Post B5i8EBGnFXvX05nmBE by azonenberg@ioc.exchange
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 (DIR) Post #B5i8EBGnFXvX05nmBE by azonenberg@ioc.exchange
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       Anybody familiar enough with Supermicro main board architecture to know what they're using the little Lattice CPLD for? Just IO expansion for the BMC or what?
       
 (DIR) Post #B5iE2Ow7DBrHdVtcga by th@v.st
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       @azonenberg which version?  X12 has a Mach XO root of trust that validates the BMC flash.
       
 (DIR) Post #B5iE4ztskejerD5c3c by azonenberg@ioc.exchange
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       @th The particular one I'm looking at is a X12DPi-N6 so that's probably it