Post B55CsSGEJrXrvqYpcm by cmb@cathode.church
(DIR) More posts by cmb@cathode.church
(DIR) Post #B55CsS1hBtv3CllDyC by cmb@cathode.church
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glasgow routing progress: it might fit into some business card size still (90*55mm size)i love that i can almost fit everything of the IO banks behind the connectors.
(DIR) Post #B55CsSGEJrXrvqYpcm by cmb@cathode.church
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fit check
(DIR) Post #B55CsSONpY4EL8NLKi by cmb@cathode.church
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i have a new arch nemesis: bga fanout.i already dread the consequences of my actions here...
(DIR) Post #B55CsSXbHHRKnighhQ by lethalbit@chaos.social
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@cmb My first thought here was "Aww cute, look at all the space and how few pins you have there"But I had to remember that I was just looking at some 1k+ 0.8mm things :v
(DIR) Post #B55CsUFEwVwS5M74MK by cmb@cathode.church
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nevermind, i forgor about the mounting holes, sync connector and reset button. 100*55mm it is. but then everything will fit comfy
(DIR) Post #B55DBg8Iy1TISS1KlM by cmb@cathode.church
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@lethalbit yah, it's just a ole bigge ECP5, nothing fancy here.
(DIR) Post #B55DBgTZgwU9WPyJuq by lethalbit@chaos.social
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@cmb Also also, which specific ECP5 is that, and that's HyperRAM I suspect?, You can possibly look at the Squishy hardware files and see what I did there for thatI had to play with the pinning and wiggle it a bit to get it to be semi-decent to route. but I also had 6-layers to do for it...Duno, but it's there if you want to look at it!
(DIR) Post #B55DSPa9kuuw381ie8 by lethalbit@chaos.social
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@cmb *shrug*
(DIR) Post #B55DY7Qq9Po1UkOHGy by whitequark@social.treehouse.systems
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@lethalbit @cmb when i needed this for work i gave up and paid JLC to route it haha
(DIR) Post #B55DY7cXRvAC51rcVU by lethalbit@chaos.social
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@whitequark @cmb I kinda like doing BGA fanout and routing, it's a fun puzzle, albeit frustrating at times
(DIR) Post #B55Ds3RcgYqEv6GM5o by lethalbit@chaos.social
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@cmb I guess long story short, You'll very likely need to change the ECP5 pinout a few time to get it to route cleanly, rotating the device itself even, Which itself is not too much of a problem provided you don't have too many other I/O constraints,
(DIR) Post #B55FyrlCj1KCcLnVZ2 by whitequark@social.treehouse.systems
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@lethalbit @cmb I gave up after half a hour of getting angry at kicad >.>
(DIR) Post #B55Fys0nn1nlOj5xsO by lethalbit@chaos.social
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@whitequark @cmb Yeah, that's fair, although 10 so far is leagues better, still a bunch of pain points to file down though...
(DIR) Post #B55GFK0NTnWoqmk1pI by uint8_t@chaos.social
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@lethalbit @whitequark @cmb 10 is so good 💜
(DIR) Post #B55GUSrIqPCseYiXY0 by lethalbit@chaos.social
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@uint8_t @whitequark @cmb Yee!I'm kinda sad it didn't make the release notes, but the little patch I made for bus unfolding of diff-pairs was nice to get in, huge useability improvement for large differential busses :3https://gitlab.com/kicad/code/kicad/-/merge_requests/1964
(DIR) Post #B55aHje77Hb62KkvZI by mxsparks@social.treehouse.systems
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@whitequark @lethalbit @cmb yeahhhh I’m considering doing that with Ceres
(DIR) Post #B55aHjpoPmxGccEGno by azonenberg@ioc.exchange
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@mxsparks @whitequark @lethalbit @cmb I thought ceres was like done? i gave you some feedback on the previous version and havent heard anything since
(DIR) Post #B55aXa0OjAuSlojadc by mxsparks@social.treehouse.systems
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@azonenberg @whitequark @lethalbit @cmb I’m either going to launch as-is or do “just one more spin bro” to get the full 2400MT/s out of the ddr; leaning toward the former atm and saving rev.next for a follow-on product
(DIR) Post #B55aXaDVwPOxQUs45A by azonenberg@ioc.exchange
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@mxsparks @whitequark @lethalbit @cmb if you wanna have me poke at the ddr routing for a bit i might be able to tune it more?