Post B4MJHW6F2WQIgo1f04 by azonenberg@ioc.exchange
 (DIR) More posts by azonenberg@ioc.exchange
 (DIR) Post #B4Lihp0bf6deYn4Oxc by azonenberg@ioc.exchange
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       Look what the intern did to this poor SOIC!First they forgot to put a soldermask aperture on one of the pads (challenge 6). While trying to rework it, they lifted the adjacent pad (challenge 07).
       
 (DIR) Post #B4LjAEldUBc4YbcKFk by Lunaphied@provably.online
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       @azonenberg nooooooooo (also what's this challenge?)
       
 (DIR) Post #B4LjAEwyo0gf7mvNw0 by azonenberg@ioc.exchange
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       @Lunaphied I'm refreshing the ReworkCTF to use modern components, add some new challenges, and fix some problems with the previous version.It's a from-scratch recreation but follows the same basic idea of a board full of problems (some simulating fabrication defects like dust specks on photomasks or incomplete etching, others simulating design errors or post-assembly damage. Each problem is documented, there's no debugging or reverse engineering involved, your goal is simply to rework the issue and make the board work again.
       
 (DIR) Post #B4LjEnqN0yYOVF0bQG by azonenberg@ioc.exchange
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       @Lunaphied They range in difficulty from 100 points (reconnecting a broken surface trace) to 500 points (adding a missing via under a BGA that wasn't discovered until the board was already populated).
       
 (DIR) Post #B4LuCtDf9jtI5lC5CK by litchralee_v6@ipv6.social
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       @azonenberg @Lunaphied I have to know: how on earth does the latter get detected, short of an X-ray or partially depopulating the board in question?
       
 (DIR) Post #B4MJHW6F2WQIgo1f04 by azonenberg@ioc.exchange
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       @litchralee_v6 @Lunaphied on the real board that inspired this challenge, it was a schematic error (the via was breaking out the wrong signal and the correct signal was unconnected).
       
 (DIR) Post #B4MMmWdlNZMvCpBP8K by litchralee_v6@ipv6.social
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       @azonenberg @Lunaphied Oh, I misunderstood. I thought the challenge was being given a physical, populated board and having to diagnose the issue from that alone. Having the schematic makes a lot more sense, and more tractable lol
       
 (DIR) Post #B4MOcM3e4ODZOgZDjU by azonenberg@ioc.exchange
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       @litchralee_v6 @Lunaphied You get the full kicad files, this is a rework challenge not a debug one
       
 (DIR) Post #B4MOeILsoq6mU01Tou by azonenberg@ioc.exchange
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       @litchralee_v6 @Lunaphied Some of these problems like inner layer trace edits are challenging enough as-is, finding the bug is a whole other can of worms