Post B4Ct1xKbg9bnHb1cES by azonenberg@ioc.exchange
(DIR) More posts by azonenberg@ioc.exchange
(DIR) Post #B4CnVrEuIGRFLrEZf6 by azonenberg@ioc.exchange
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Years ago I had a "ReworkCTF" board with 20-odd PCB layout bugs designed into it on purpose, ranging from backwards LEDs to missing vias under a BGA to inner layer differential pair swaps.The original board had some design issues that made some of the fixes easier/harder than intended, and also ancient, I think now EOL, parts (a Spartan-3A FPGA - even if not EOL nobody wants to use one of those in 2026).I'm hoping to do a gen 2 of the challenge soon probably based on a BGA STM32 or Spartan-7 but haven't worked out the specifics yet.Is anybody interested in contributing challenge concept based on real board bugs you've had?Also, would folks be interested in me livestreaming a "play through" of some/all of the challenges once I have a board in hand?
(DIR) Post #B4CquLGYbfq9I2NA1o by jpm@aus.social
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@azonenberg hell yes! IMHO in some ways doing this on a FPGA platform is easier because you can just swap TX/RX et al in gateware, so I’d probably choose a MCU platform with deranged IO restrictions. The single nastiest prototype board bug I’ve ever done to myself is an I2C SDA/SCL swap where the ATSAME51 could swap SDA/SCL between the pins but only by using a different SERCOM, and that other SERCOM was being used for something else and there was no other SERCOM that could drive the OTHER pins. I’ve been bitten by this on a few different ATSAM* family SERCOM configuration restrictions. Another good* one is a simple voltage divider from a battery, but going to a digital-only pin instead of an analogue-capable pin. Also using resistor values far too high in the M-ohm range so that the ADC’s sample and hold circuit doesn’t have enough time to settle even at the slowest acquisition clock. The classic “oops I forgot pull-ups” is always fun, and more subtle is not including series resistors on 10+ MHz data lines. Depending on the MCU, USB differential pairs might be a fun one. Doesn’t matter for low speed USB, doesn’t really matter much for full speed, starts to matter for high speed USB2. And for an extra level of hell, use a WCH MCU with atrocious documentation.
(DIR) Post #B4Cr91mFLdtXBqCJlI by azonenberg@ioc.exchange
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@jpm this is specifically a rework/repair technician challenge not a debug challenge (although that might also be fun, it's a separate skill).All of the defects will be well understood and documented. Your job is to apply the necessary ECO to make the board work as expected.
(DIR) Post #B4CrF6BlrHiybt20kS by azonenberg@ioc.exchange
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@jpm so something like "missing pullup" is fine but the backstory of what the signal does is irrelevant. For the challenge it'd just be a weak on die pulldown configured on a GPIO that declares pass once it goes high.
(DIR) Post #B4CswmDPa47XMKBpx2 by jpm@aus.social
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@azonenberg aha gotcha! Definitely include some 0.2mm traces that are crossed to see how good the bodge-work is. Paging @ThermiteBeGiants got any nasty suggestions of re-works?
(DIR) Post #B4Ct1xKbg9bnHb1cES by azonenberg@ioc.exchange
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@jpm @ThermiteBeGiants Oh the swapped diffpair is gonna be 0.125mm which is min feature size for oshpark. Not much of a challenge if it's big
(DIR) Post #B4CvvNWcC0tsMACHLc by ThermiteBeGiants@aus.social
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@azonenberg @jpm I recently had to do a rework on a prototype board where I drilled into a via and soldered a bridge wire from it to an 0402 resistor. If you want a challenge for your board, add on having to move that 0402 around so that it’s only on one of the original pads before your solder the bodge wire to the via
(DIR) Post #B4DK1n9sCS5uUg9PV2 by tj@altelectron.org.uk
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@azonenberg @jpm I have this from Congress two years ago. I think there’s demand.
(DIR) Post #B4DK1nRF9rzNMYHHZg by azonenberg@ioc.exchange
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@tj @jpm yep i think that was... cpresser? who took my concept and ran with it to be a bit more newbie friendly and lower cost.
(DIR) Post #B4DWYf8AGY7cbRn9xA by tj@altelectron.org.uk
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@azonenberg @jpm yeah looks to be, more boards for challenges with documented test stages would be great.The smd soldering kits from china are helpful for learning, but they don't have any mid steps. It either works or doesn't and that isn't the best for figuring out what you did wrong.
(DIR) Post #B4DWYfRJ7NQzYokRn6 by cccpresser@chaos.social
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@tj @jpm @azonenberg exactly. The main idea was to make a challenge board that is not super frustrating for beginners. And has lower requirements regarding tools and materials.https://gitlab.aachen.ccc.de/cpresser/reworkctf-pico/-/blob/main/docs/Challenges.md?ref_type=headsThis was after I solved Andrews version and was not to happy with my own results :)I am considering to make more of them (they are "sold out"), but have not yet decided if I want to add more challenges or edit challenges.
(DIR) Post #B4DWYfdMOZ4kACO4Zs by azonenberg@ioc.exchange
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@cccpresser @tj @jpm well I'm planning to do a rev2 in the next month or so, then livestream a playthrough
(DIR) Post #B4DcK50aN18yF6g0ie by craigjb@fosstodon.org
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@azonenberg I thought I had more bodge pics, but here are a couple real ones1st pic is wrong crystal footprint would be good. On this board I swapped the two gnd pads with the out and vcc pads. On a non-symmetric footprint too. 2nd pic is a bodged missing protection diode on a SOT transistor
(DIR) Post #B4DdDdgV9B2LiQm7CS by cccpresser@chaos.social
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@azonenberg @tj @jpm in that case, I will wait to see your rev2 and copy the new challenges and ideas that fit the "accessible" format as well.My rough goal is to have a new version of my variant available for emfcamp.
(DIR) Post #B4E5kzYLeuKroQeafY by natanbc@mastodon.social
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@azonenberg Small one: DRC never complained (IIRC) about that ground pour being disconnected from the rest