Post ApqvAaFvsyLQPEKPEO by bentsukun@mastodon.sdf.org
(DIR) More posts by bentsukun@mastodon.sdf.org
(DIR) Post #Appho9r5rvkNaoj5Si by lanodan@queer.hacktivis.me
2025-01-07T08:20:58.446315Z
0 likes, 0 repeats
VisionFive2 (riscv): Boots nicely with regular Alpine LinuxRockPro64 (arm64), even after flashing Tow-Boot: NopeHow come a much newer board on the rather experimental architecture that's riscv causes me less issues…
(DIR) Post #Appi1rHLjUD626XXl2 by lanodan@queer.hacktivis.me
2025-01-07T08:23:26.708077Z
0 likes, 0 repeats
That said I think it's mostly that Starfive actively mainlined pretty everything already (hence why I bought it), while Pine64 well… not really.
(DIR) Post #AppiLukkWdIQbEr4ee by lanodan@queer.hacktivis.me
2025-01-07T08:27:03.593615Z
0 likes, 0 repeats
@kura riscv probably couldn't be more open.Meanwhile arm, specially in practice is rather closed.
(DIR) Post #AppkFYQko5GjXRb69I by piggo@piggo.space
2025-01-07T08:38:04.622331Z
0 likes, 0 repeats
@lanodan @kura arm itself is completely open (well you can't make your own chips with it for free but all the docs are there). Vendor extensions aren't and that is the same with riscv, no?
(DIR) Post #AppkFZMtJvm0RknWlc by lanodan@queer.hacktivis.me
2025-01-07T08:48:18.211984Z
1 likes, 0 repeats
@piggo @kura Well I've yet to see NDAs and firmware blobs on the riscv side of things at least, while arm is full of that stuff.That said for me the difference is more that StarFive actively mainlines to OpenSBI, u-boot, and linux (and is like 90% done): https://rvspace.org/en/project/JH7110_Upstream_PlanMeanwhile Pine64… lol, and it's so typical of ARM devices to just ship with vendor software and not care about mainlining any of their stuff.
(DIR) Post #AppoT9nDbbHgzrqYQS by eragon@pl.eragon.re
2025-01-07T09:26:20.989489Z
0 likes, 0 repeats
@piggo From what I understood of RISC-V is that you don't even need a licence to make a chip. You can just grab the spec and start making your own silicon (if you have a fab).And all the tools to run something on a chip are free and without blobs.@kura @lanodan
(DIR) Post #AppoTAtzTuIORA1TcW by piggo@piggo.space
2025-01-07T09:29:03.675942Z
0 likes, 0 repeats
@eragon @kura @lanodan obviously, but you won't get far with just the ISA, vendors license IP blocks from someone who developed them and thats where the NDA and blobs shit comes from. I dont see how the ISA being open would prevent that, other than just being so new this didn't have time to appear yet
(DIR) Post #AppoTBqTyR5FMZOBn6 by lanodan@queer.hacktivis.me
2025-01-07T09:35:28.031696Z
0 likes, 0 repeats
@piggo @kura @eragon riscv isn't just an ISA though, like boot and device discovery is standardized: https://github.com/riscv-non-isa/riscv-brsMeanwhile yeah, arm is the one that frequently is just a lonely CPU on a board with no boot chip.
(DIR) Post #ApppbSzKDo0gni2Gye by eragon@pl.eragon.re
2025-01-07T09:47:56.439725Z
1 likes, 0 repeats
@lanodan @kura @piggo Yup, RISC-V is more than just an ISA it's an ecosystem.And that's what makes all the difference.Also the fact that there are so many different members backing RISC-V gives me hope that if one of them tries to steer too much into NDAs and blobs the others will force them to stop.Intel, Nvidia, Qualcomm they all have made blobs for some of their other products. But you also have the Brazilian Gov, SciFive, Arduino, AMD, Raspberry, and way more.
(DIR) Post #Appt3CGAJJzctCpKQS by lanodan@queer.hacktivis.me
2025-01-07T10:26:55.975787Z
0 likes, 0 repeats
@kura @piggo @eragon Yeah I'd more count on SiFive and StarFive for good riscv SoCs.Which is already more than ARM where the only ones that seem good are NXP, with RockChip being sometimes okay, and then horrors like Allwinner not even publishing the source code of their u-boot and linux kernel trees.
(DIR) Post #ApqvAaFvsyLQPEKPEO by bentsukun@mastodon.sdf.org
2025-01-07T18:03:52Z
1 likes, 0 repeats
@lanodan Let me introduce you to the way audio output works on the Raspberry Pi 3. Hint: if you configure a GPIO pin as using hardware PWM, the headphone output stops working.