Post AErpmD6oyGYHYbTSHA by alvarezp@mastodon.xyz
(DIR) More posts by alvarezp@mastodon.xyz
(DIR) Post #AEpmbcv7yaeEFILXUW by wolf480pl@mstdn.io
2021-12-27T16:07:04Z
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Latches vs flip-flops?
(DIR) Post #AEpmxjEfB4IwCc1U92 by wolf480pl@mstdn.io
2021-12-27T16:11:03Z
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should probably clarify that it's an electronics question but then probably nobody would vote...
(DIR) Post #AEpnfk6BKU2nca2kIy by sjb@mstdn.io
2021-12-27T16:19:01Z
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@wolf480pl they're types of shoes
(DIR) Post #AEpnrUXezkaaqcUyCu by wolf480pl@mstdn.io
2021-12-27T16:21:08Z
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@sjb that too, it's an interesting confounder.But I meant https://en.wikipedia.org/wiki/Flip-flop_(electronics)with latches being async, level-triggered and flip-flops being sync, edge-triggered
(DIR) Post #AErhwo1bm3SZJQZqPw by alvarezp@mastodon.xyz
2021-12-28T14:24:15Z
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@wolf480pl I voted Depends. It depends on what is the question.
(DIR) Post #AErhzUjdwvJmM4SM6K by wolf480pl@mstdn.io
2021-12-28T14:24:47Z
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@alvarezp which of the two would you rather use in a digital circuit?
(DIR) Post #AErltvEUv0YscCUDse by alvarezp@mastodon.xyz
2021-12-28T15:08:34Z
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@wolf480pl Depends on what the digital circuit should do.
(DIR) Post #AErmnGRvjkwkLQ9tey by alvarezp@mastodon.xyz
2021-12-28T15:18:34Z
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@wolf480pl I remember implementing a latch-like circuit using flip-flops because I didn't know how to use a latch, but disliking having to add an otherwise useless high-frequency clock. But if you already have a clock, why is a latch? I think it will all depend on the use case.
(DIR) Post #AErn3engy62kV89cdU by wolf480pl@mstdn.io
2021-12-28T15:21:33Z
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@alvarezp when I was at uni, my FPGA teacher was like, "If you make a cyclic dependency in @* instead of @(posedge clk), you'll make a latch. Don't do that."Because in FPGAs you already have a clock, so making a latch would be silly, as you said.But I'm wondering if there maybe is a legit situation where one might need a latch despite having a clock, or where having a clock wouldn't be helpful at all as a latch is needed anyway.
(DIR) Post #AErpmD6oyGYHYbTSHA by alvarezp@mastodon.xyz
2021-12-28T15:51:58Z
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@wolf480pl Maybe if you can't rely on that clock or if you have multiple clocks, or maybe if the input is external and can't be guaranteed to be held until the next clock edge so you may need to latch it. That's why I don't think it's latches vs flip-flops, just use what you need to use.
(DIR) Post #AErqnMhisjIJYlqhpg by wolf480pl@mstdn.io
2021-12-28T16:03:25Z
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@alvarezp for external inputs we'd just pipe them through 2-3 flip-flops hoping it'd be enough that the metastability won't get through... but I guess in some situations that may be too slow
(DIR) Post #AErrnnJ64ag01N6CNU by alvarezp@mastodon.xyz
2021-12-28T16:14:41Z
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@wolf480pl Why 2-3?
(DIR) Post #AErs9aWyFtVylcyr4K by wolf480pl@mstdn.io
2021-12-28T16:18:38Z
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@alvarezp if the external signal changes too close to the clock, the first flip-flop may become metastable. Let's say there's p chance this will happen.If this happens, the metastable state should decay after some time and turn into a 1 or a 0. Let's say there's q chance this will happen before the next clock's t_setup.The chance that the second flop will become metastable is p*(1-q).If we add a third flop, the chance that it'll become metastable is p*(1-q)*(1-q).More flops - lower chance
(DIR) Post #AErtywWGMUrZgchWhE by wolf480pl@mstdn.io
2021-12-28T16:38:34Z
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@alvarezp and I was told that it is known from experience that 2 is ok, and 3 is definitely enough.
(DIR) Post #AErwfQ6cwxVbWC5nn6 by alvarezp@mastodon.xyz
2021-12-28T17:09:11Z
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@wolf480pl This is quite interesting. I didn't get that far.
(DIR) Post #AErxKkRSFKSqShXbwu by wolf480pl@mstdn.io
2021-12-28T17:16:40Z
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@alvarezp see also https://electronics.stackexchange.com/questions/237725/how-does-2-ff-synchronizer-ensure-proper-synchonization