Post 1010271 by slp@mstdn.io
 (DIR) More posts by slp@mstdn.io
 (DIR) Post #1008805 by MochiWaifu@slime.global
       2018-11-06T12:47:15Z
       
       1 likes, 1 repeats
       
       ah, AMD is gonna talk about their new EPYC chips later and... it's gonna get interesting as heck64 cores... 128 threads... 👀
       
 (DIR) Post #1008911 by phryk@mastodon.social
       2018-11-06T12:54:35Z
       
       0 likes, 0 repeats
       
       @MochiWaifu Wait, AMD is releasing serious RISC hardware? o_O
       
 (DIR) Post #1008912 by feld@bikeshed.party
       2018-11-06T12:59:09.376868Z
       
       0 likes, 0 repeats
       
       @phryk @MochiWaifu IIRC, modern CISC CPUs are actually RISC inside 😅
       
 (DIR) Post #1009911 by phryk@mastodon.social
       2018-11-06T13:00:51Z
       
       0 likes, 0 repeats
       
       @feld Wait, so they implement an abstract CISC CPU *on top* of RISC hardware?Whenever I even so much as glance at processors, they seem to get worse… 🤮 @MochiWaifu
       
 (DIR) Post #1009912 by feld@bikeshed.party
       2018-11-06T14:20:04.719008Z
       
       0 likes, 0 repeats
       
       @phryk @MochiWaifu yes, that's my understanding. it's emulated CISC in the microcode.
       
 (DIR) Post #1010271 by slp@mstdn.io
       2018-11-06T14:35:26Z
       
       0 likes, 0 repeats
       
       @feld @phryk @MochiWaifu The line between CISC and RISC, which was never clearly defined, is now fuzzier than ever. Can the ARMv8 ISA be considered RISC?That's why some people consider that those terms are already obsolete.
       
 (DIR) Post #1010272 by feld@bikeshed.party
       2018-11-06T14:38:25.114265Z
       
       0 likes, 0 repeats
       
       @slp @MochiWaifu @phryk I thought it was very clearly defined. RISC instructions always took exactly one clock cycle.