Posts by dlharmon@chaos.social
(DIR) Post #B4w7Devu3GT1AS8pwe by dlharmon@chaos.social
0 likes, 0 repeats
Anything else I should throw in? I considered an XC3S or XC6S part but the XC7A covers most of that code. The cost is about 5x what I remember paying in the past too. I bought the Gatemate and SU+, everything else on here is leftovers or harvested from scrap.There will be a header for expansion.I'm probably going to put a bunch of U.fl coax connectors on IO. Especially the SERDES on the Gatemate. Might throw an SFP+ on the XCZU.
(DIR) Post #B4w7DfTw0jgms040zQ by dlharmon@chaos.social
0 likes, 0 repeats
I don't have a normal Ultrascale+ part on here but that code is well covered by the ZU+, SU+, XC7A. Also, I use US+ heavily so any issues would get caught in my day to day usage.
(DIR) Post #B54PahctYYdocZ4GEC by dlharmon@chaos.social
0 likes, 0 repeats
Making a footprint for a Mini-Circuits SMIQ-6243H+, I noticed Weight: 0.04 grams on the package drawing.$2,025,000 per kg.I've used some bare die parts that would certainly work out higher than that.
(DIR) Post #B5q602XIHPZLDOKR2O by dlharmon@chaos.social
0 likes, 0 repeats
Apparently, I'm writing a BSDL parser in Rust.Know of any permissively licensed BSDL files I can ship with the parser for unit test purposes?I've got a whole bundle of them including every Xilinx device with JTAG from XC4000 to Versal but none suitably licensed.
(DIR) Post #B5q7np0ewck9hHMjw0 by dlharmon@chaos.social
0 likes, 0 repeats
@whitequark @azonenberg Interesting thought. Cologne Chip (Germany) doesn't have a copyright statement on their BSDL for Gatemate so that may be the case.I may end up editing that as a base for a fake test BSDL probably with a DEC or Cray JEP106 code.
(DIR) Post #B5q7npK9m8L6fkUJKC by dlharmon@chaos.social
0 likes, 0 repeats
@whitequark @azonenberg They actually do. Vscodium was hiding the first line from me when I did "$ more ccgm1a1_fbga324.bsd".I'm just going to make up a fake file.
(DIR) Post #B5zT7sDeZGRCu3UAXQ by dlharmon@chaos.social
0 likes, 0 repeats
@azonenberg Assuming a 5 M cable will reach and you only need 2.0 HS, passive should be fine and in spec. There are some 10 M ones with a lump in the middle that's just a USB hub. The 5 m limit is due to latency not loss.Edit: on 2.0.
(DIR) Post #B6PONJJQfd0Rc7geDQ by dlharmon@chaos.social
0 likes, 0 repeats
Back to working on the BSDL parser which is turning out to be a bigger project than I originally anticipated. So many corner cases due to the fact that it's VHDL based and the standard allows a lot of variation. Quite a bit of code for port vectors which are only used by 3 of the ~3100 BSDLs I'm testing on. Those 3 are ancient, from 1994-2000 era parts.Maybe I shouldn't be going for completeness.There's a pretty small subset of BSDL used by vendors today.
(DIR) Post #B6PONJibA38gsBSkRk by dlharmon@chaos.social
0 likes, 0 repeats
I'm also a bit surprised by a few things in the BSDLs. The TAP_SCAN_CLOCK of many Xilinx parts doesn't correspond to the datasheet Ftck max. XCVU parts have 66 MHz in the BSDLs, datasheet says 20 MHz for all but a few that only have one SLR. XCZU is 30 MHz in the BSDLs, 15 or 25 MHz in the datasheets depending on speed grade. XC6 goes the other way with much lower frequencies in the BSDLs than datasheets.Annoying because I'd hoped to automate selection of a lower TCK if required based on that.
(DIR) Post #B6PONK3rsy9Xw9PjbE by dlharmon@chaos.social
0 likes, 0 repeats
Some of the older Xilinx BSDLs are unusual. Here we have don't care bits in most of the IDCODE including all of the manufacturer bits of an old Coolrunner CPLD. Some of the earliest Xilinx parts with JTAG don't even have an IDCODE.I validate the IDCODE register for compliance, these fail as X is interpreted as 0 for that check. Maybe I'll pull that out or maybe just delete these few files.
(DIR) Post #B6PORatlECWhJXiu8W by dlharmon@chaos.social
0 likes, 0 repeats
@azonenberg Interesting. I didn't know that. Almost curious enough to get a chip and see what it spits out.
(DIR) Post #B6cvtUdbv929Y3YjTc by dlharmon@chaos.social
0 likes, 0 repeats
@azonenberg For N instances, do starting phases of rate*i, increment phase by N*rate in each instance?For long running sine generation, I always use integers for phase, scale such that integer overflow does the mod 2*pi for me.
(DIR) Post #B6hACRwgoECU3Q0Tmi by dlharmon@chaos.social
0 likes, 0 repeats
@azonenberg Similar feelings here.My objections to Altera now mostly apply to Xilinx as well. If/when I get to pick an FPGA for a client and it has to be high end, I'll probably let both quote parts where I would have asked for Xilinx only before.For my personal projects, the gray market KU5Ps and AU10Ps from distributors will go a long way. I don't need Kintex US+ Gen 2 for any reason.I'm evaluating Colognechip for low end with 5 Gb transceivers. Docs are lacking, probably software too.
(DIR) Post #B6pSXoFeQNMDkstFAm by dlharmon@chaos.social
0 likes, 0 repeats
Spent a bit of time looking at Efinix Topaz and Titanium docs.It seems Topaz is simply a marketing name for a lower speed grade Titanium. Tz50, Ti35 and Ti60 have the same bitstream length, are likely the same die. Likewise for Ti375, Ti240, Ti165, Tz200, Tz325.The duplication of identical documentation makes more work for the user. Separate datasheet for each chip, separate primitive docs for, Tz, Ti.I'm still open to using the parts but feels like a Spartan-3, Cyclone-4 hybrid on 16 nm.
(DIR) Post #B6pSXoSldbqiPZ1icK by dlharmon@chaos.social
0 likes, 0 repeats
There are definitely some things to like. The quad Risc-V on some parts will be quite useful, seems to be well done. Also the LPDDR4X controller. I think they have done the pinout such that it can be routed on 6 layers. LPDDR4X availability is decent as well with some second tier memory suppliers like Winbond making lower density parts.I have to wonder what's the reason behind the 4-LUT CLB with no distributed RAM. They should have at least thrown in some shallow memories to compensate.
(DIR) Post #B6pSXohIlZTX8dpKGu by dlharmon@chaos.social
0 likes, 0 repeats
Virtex-5 is 20 years old so any patents should be expired. It was the first 6-LUT Xilinx. Hopefully for the next generation, Efinix can go to a CLB closer to that.
(DIR) Post #B6pSXouPyny1nJxniS by dlharmon@chaos.social
0 likes, 0 repeats
I'd been leaning toward Xilinx Ultrascale+ for Wren (phase noise analyzer), specifically AU10P or KU5P in the FFVB676 package which is excessive but not terribly expensive when purchased gray market.Given the Vivado licensing changes, relatively low needs of Wren, rising gray market prices, I'm considering alternative FPGAs.If I'd be willing to drop 10 Gb Ethernet, the ability to stream full sample rate, Tz50 is appealing. The only transceiver Efinix currently available is Ti375, about $250.
(DIR) Post #B6pSXrMqq3tpQ5HXJQ by dlharmon@chaos.social
0 likes, 0 repeats
I think my most practical options for Wren at this point are either Tz50F256C2 ($33 at Digikey), a connector to export full sample rate over 8 LVDS pairs to the FPGA in a Mockingbird plus 1000BASE-T Ethernet only supporting narrowband data and short snapshots. Would have to modify many of my DSP functions to use it. Would be able to use standalone or in a Mockingbird chassis.XCAU7P-1SBVC484E ($74 Avnet, backordered or $89 Digikey), 10 Gb Ethernet.
(DIR) Post #B6pl4DKoV0sJzVuEtc by dlharmon@chaos.social
0 likes, 0 repeats
The Efinix decoupling guidelines are ridiculous. Here's the Tz50 in the 256 ball 0.8 mm BGA.I'll be ignoring this. several 470 nF 0201s under the BGA, several 10 uF 0402 nearby outside the grid, where space allows, 2x 47 uF 0805 at the regulator.
(DIR) Post #B6pl4Dza3RU81wynRI by dlharmon@chaos.social
0 likes, 0 repeats
@whitequark By "a crackhead" you mean Analog Devices.