Post B9nj5q2PIP492dCjse by spycrab@kolektiva.social
 (DIR) More posts by spycrab@kolektiva.social
 (DIR) Post #B9niGjgDAuwQYOSHSK by spycrab@kolektiva.social
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       Ok fedi I want to get y'all's guys input on something. Oh, and boost would be appreciated!  What would y'all want to see in a open source RISC ISA (something to either replace or work alongside RISC-V)?I'll put some of the things I've already heard in the replies.
       
 (DIR) Post #B9niGjwWCHz9My5IsC by spycrab@kolektiva.social
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       32,64,128 bit address space support (kinda a no brainer at this point).Fix length 32 bit instructions.High levels of hardware security support.Modularity is cool but it should not be SO modular that the standard is confusing or weak.And...what else; what do y'all think?
       
 (DIR) Post #B9niGkEx5kjMI8i1bc by kumicota@akkoma.kumicota.moe
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       @spycrab A proper bios with ACPI and more that doesn't rely on device tree
       
 (DIR) Post #B9nj5q2PIP492dCjse by spycrab@kolektiva.social
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       @kumicota I thought that was a software aspect. I didn't know the BIOS was hardware related (I'm pretty new to all this stuff)
       
 (DIR) Post #B9nj5qP5w3DKAzorFA by kumicota@akkoma.kumicota.moe
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       @spycrab ohh, I read the text wrong, nvm and my bad
       
 (DIR) Post #B9njDFb0faTUKrvM2a by spycrab@kolektiva.social
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       @kumicota oh good I was worried I really didn't know what I was doing, lol.That's all good 😊
       
 (DIR) Post #B9u2Xu8IjCKjvaojtg by astraleureka@social.treehouse.systems
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       @spycrab honestly, REDUCED modularity is what would be a big winner. riscv is modular to the point of being an absolute shitshow disaster lemme get uhhh rv64gc_zicsr_zifencei_zicntr_zihpm_zicond_zicbom_zicbop_zicboz_zicbfps_zihintpause_zihintntl_zawrs_zacas_zabha_zama16b_ztso_zfa_zfh_zfhmin_zfbfmin_zfinx_zdinx_zhinx_zhinxmin_zca_zcb_zcd_zcf_zcmp_zcmt_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh_zkr_zkt_zkn_zks_svadu_svade_svinval_svnapot_svpbmt_svbare_sha_shcounterenw_shvstvala_shtvala_shvstvecd_shvsatpa_sstc_sscofpmf_ssccfg_ssccptr_ssstateen_ssaia_smaia_smstateen_smepmp_smcdeleg_v_zve32x_zve32f_zve64x_zve64d_zvfh_zvfhmin_zvfbfmin_zvfbfwma_zvbb_zvbc_zvkb_zvkg_zvkned_zvknha_zvknhb_zvksed_zvksh_zvkt_zvkn_zvknc_zvkng_zvks_zvksc_zvksg_zvl32b_zvl64b_zvl128b_zvl256b_zvl512b_zvl1024b_zvl2048b_zvl4096bstatements dreamed up by the utterly deranged riscv architecture specification authors
       
 (DIR) Post #B9u2dxVf5Oq28ddBs8 by spycrab@kolektiva.social
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       @fogti @xerz what is loongarch and why does it need 2 'o's (I'll figure out soon enough,lol)
       
 (DIR) Post #B9u2dxkCDMSqriQnWi by astraleureka@social.treehouse.systems
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       @spycrab @fogti @xerz in short it's literally mips but they changed the encoding a little bit so it didn't look like they copied their homeworkit's alright, very stereotypical mips though
       
 (DIR) Post #B9u2iq7hyYiOg5kq6S by fogti@chaos.social
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       @astraleureka @spycrab @xerz MIPS died and LoongArch is the successor
       
 (DIR) Post #B9u2nYQxAlbvGL0Kdk by astraleureka@social.treehouse.systems
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       @fogti @spycrab @xerz yeah that's a pretty reasonable description