Post B6pl4DowgyyhUy0IrY by whitequark@social.treehouse.systems
 (DIR) More posts by whitequark@social.treehouse.systems
 (DIR) Post #B6pSXoFeQNMDkstFAm by dlharmon@chaos.social
       0 likes, 0 repeats
       
       Spent a bit of time looking at Efinix Topaz and Titanium docs.It seems Topaz is simply a marketing name for a lower speed grade Titanium. Tz50, Ti35 and Ti60 have the same bitstream length, are likely the same die. Likewise for Ti375, Ti240, Ti165, Tz200, Tz325.The duplication of identical documentation makes more work for the user. Separate datasheet for each chip, separate primitive docs for, Tz, Ti.I'm still open to using the parts but feels like a Spartan-3, Cyclone-4 hybrid on 16 nm.
       
 (DIR) Post #B6pSXoSldbqiPZ1icK by dlharmon@chaos.social
       0 likes, 0 repeats
       
       There are definitely some things to like. The quad Risc-V on some parts will be quite useful, seems to be well done. Also the LPDDR4X controller. I think they have done the pinout such that it can be routed on 6 layers. LPDDR4X availability is decent as well with some second tier memory suppliers like Winbond making lower density parts.I have to wonder what's the reason behind the 4-LUT CLB with no distributed RAM. They should have at least thrown in some shallow memories to compensate.
       
 (DIR) Post #B6pSXohIlZTX8dpKGu by dlharmon@chaos.social
       0 likes, 0 repeats
       
       Virtex-5 is 20 years old so any patents should be expired. It was the first 6-LUT Xilinx. Hopefully for the next generation, Efinix can go to a CLB closer to that.
       
 (DIR) Post #B6pSXouPyny1nJxniS by dlharmon@chaos.social
       0 likes, 0 repeats
       
       I'd been leaning toward Xilinx Ultrascale+ for Wren (phase noise analyzer), specifically AU10P or KU5P in the FFVB676 package which is excessive but not terribly expensive when purchased gray market.Given the Vivado licensing changes, relatively low needs of Wren, rising gray market prices, I'm considering alternative FPGAs.If I'd be willing to drop 10 Gb Ethernet, the ability to stream full sample rate, Tz50 is appealing. The only transceiver Efinix currently available is Ti375, about $250.
       
 (DIR) Post #B6pSXpFKj2hIqBkVJg by mossmann@mastodon.social
       0 likes, 0 repeats
       
       @dlharmon For me, I think 10 Gb Ethernet would be an anti-feature anyway.
       
 (DIR) Post #B6pSXpQg2rltPN3Yzw by dlharmon@chaos.social
       0 likes, 0 repeats
       
       @mossmann I can see that, might include 1000BASE-T in addition to the SFP+ if I go that route.
       
 (DIR) Post #B6pSXpaFTHQZt3XCuu by azonenberg@ioc.exchange
       0 likes, 0 repeats
       
       @dlharmon @mossmann i always dual track Ethernet on my designs like that, a baseT phy plus SFP.
       
 (DIR) Post #B6pSXrMqq3tpQ5HXJQ by dlharmon@chaos.social
       0 likes, 0 repeats
       
       I think my most practical options for Wren at this point are either Tz50F256C2 ($33 at Digikey), a connector to export full sample rate over 8 LVDS pairs to the FPGA in a Mockingbird plus 1000BASE-T Ethernet only supporting narrowband data and short snapshots. Would have to modify many of my DSP functions to use it. Would be able to use standalone or in a Mockingbird chassis.XCAU7P-1SBVC484E ($74 Avnet, backordered or $89 Digikey), 10 Gb Ethernet.
       
 (DIR) Post #B6pl4DKoV0sJzVuEtc by dlharmon@chaos.social
       0 likes, 0 repeats
       
       The Efinix decoupling guidelines are ridiculous. Here's the Tz50 in the 256 ball 0.8 mm BGA.I'll be ignoring this. several 470 nF 0201s under the BGA, several 10 uF 0402 nearby outside the grid, where space allows, 2x 47 uF 0805 at the regulator.
       
 (DIR) Post #B6pl4DbTV4CcpBhXrk by whitequark@social.treehouse.systems
       0 likes, 0 repeats
       
       @dlharmon 1 nF
       
 (DIR) Post #B6pl4DowgyyhUy0IrY by whitequark@social.treehouse.systems
       0 likes, 0 repeats
       
       @dlharmon needs a few 100 pF ones for that "a crackhead definitely wrote this" feeling
       
 (DIR) Post #B6pl4Dza3RU81wynRI by dlharmon@chaos.social
       0 likes, 0 repeats
       
       @whitequark By "a crackhead" you mean Analog Devices.
       
 (DIR) Post #B6pl4E6fd59kNwISUS by whitequark@social.treehouse.systems
       0 likes, 0 repeats
       
       @dlharmon perfect, no notes
       
 (DIR) Post #B6pl4EGF3UoQrcm6PQ by azonenberg@ioc.exchange
       0 likes, 0 repeats
       
       @whitequark @dlharmon Lol. Yeeeah 1 nF caps for an FPGA sounds ludicrous.Looking at the Ti375 dev board schematics I see a *slightly* saner approach: the DDR has a 47 and 10 uF per rail, plus a ton of 0.1s and a handful of 0.01s. I still doubt they did any proper PDN simulations but it beats what you showed.The FPGA core is similar, 100 / 47 / 1 / 0.1 and a few 0.01s. I suspect the 100 and 47 might have some nasty resonant peaks.But at least no 1 nF
       
 (DIR) Post #B6pld2ttHkm1lVvEoa by dlharmon@chaos.social
       0 likes, 0 repeats
       
       @azonenberg @whitequark Interesting. Seems they ignored their own guidelines there or changed them after designing that board. Ti375 N1156 calls for 1 nFs.
       
 (DIR) Post #B6pljxoObSHa0hePJI by azonenberg@ioc.exchange
       0 likes, 0 repeats
       
       @dlharmon @whitequark on my next large fpga design i want to try stuffing a second board on my friend's pnp with no fpga, and doing 2 port shunt through measurements on the pdn to actually measure impedance
       
 (DIR) Post #B6pumZFnGVCQIimYzo by ftg@mastodon.radio
       0 likes, 0 repeats
       
       @azonenberg @dlharmon @whitequark The results of that would certainly be interesting to see.