Post B6h9oxBszNdG0cuXgm by ldcd@social.treehouse.systems
(DIR) More posts by ldcd@social.treehouse.systems
(DIR) Post #B6h60Iwg2vcYqgxE00 by azonenberg@ioc.exchange
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Just ordered an Efinix Ti375 devkit to play with their SERDES. This will be my first time using transceivers on a non-Xilinx part, but the way Vivado is headed these days I want to have an off-ramp.I'm not leaving Xilinx in the immediate future, I have a lot of existing component inventory to use up, but I don't see using any of their newer generation parts in the future.
(DIR) Post #B6h89RDkqbfD1sQPYm by ldcd@social.treehouse.systems
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@azonenberg is my read that the Tz series is the same fabric as the Ti just smaller correct?
(DIR) Post #B6h89ROkBkSDZxZBgm by azonenberg@ioc.exchange
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@ldcd unsure have only used trion to date
(DIR) Post #B6h8eK9NBb1C4q6S6C by ldcd@social.treehouse.systems
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@azonenberg do you have a sense of where the larger Trions would fit in the 7 series lineup in terms of amount of logic (I know it's hard to make a direct comparison here especially given the very different processes)
(DIR) Post #B6h8eKYBhKrrJniGmG by azonenberg@ioc.exchange
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@ldcd they're also very architecturally different: no lutram hits some designs hard. Lut4 vs lut6 means different packing density depending on average fan in. Block rams are a lot smaller but you have more of them.And the 40nm low power process is a lot slower than 7 series
(DIR) Post #B6h8p7ozMeob1didLU by azonenberg@ioc.exchange
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@ldcd the hard ddr controller also means IOs you can't use for anything else if you don't need ddr, but you aren't burning fabric logic talking to memory if you do
(DIR) Post #B6h8sz6di3wZ9aobXU by ldcd@social.treehouse.systems
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@azonenberg which part did you look at? I was giving the T8 a look because it seemed like basically an ice40hx8k with a couple DSPs and ice40 prices have gone nuts
(DIR) Post #B6h8szK6tyidpN7MXI by azonenberg@ioc.exchange
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@ldcd i have a t20 devkit and a handful of t20 and t85, i think, chips but haven't made a board for them yet been too busy
(DIR) Post #B6h9094B4ln84X4uLQ by azonenberg@ioc.exchange
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@ldcd the really small ones (t4/t8) seem to be 0.5 or 0.4mm packages only and they don't have the gate capacity to be interesting to me.Everything larger can be found in an 0.8mm package
(DIR) Post #B6h91wQh1wkvSVSxLk by ldcd@social.treehouse.systems
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@azonenberg yeah I would rather have a hard DDR controller than not, (one of the reasons I was kind of excited about SUS+)
(DIR) Post #B6h91wge4dW4FyvhDM by azonenberg@ioc.exchange
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@ldcd su+ is cursed for other reasons because it's versal derived though
(DIR) Post #B6h9PusOSNrvajr3po by ldcd@social.treehouse.systems
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@azonenberg oh it's definitely one of their weirder FPGAs; at least the config engine is a riscv instead of a hard microblaze, and you can actually program it/turn it off
(DIR) Post #B6h9Pv3jmCwW9vA7W4 by azonenberg@ioc.exchange
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@ldcd the thing to keep in mind about efinix is it's a lot of off the shelf third party ip and less in house vertical integration.So less flexibility, more attention needed to pin out and board design. Not all clocks can route to all PLLs, etc.
(DIR) Post #B6h9UFHUXBBa2BetA8 by azonenberg@ioc.exchange
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@ldcd and only a small handful of ios can do lvds and iirc some of the lvds pins can't also do normal io
(DIR) Post #B6h9ZANkB0PeHtvgki by ldcd@social.treehouse.systems
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@azonenberg hmm that last one is pretty annoying
(DIR) Post #B6h9ZAievF8vKliOLw by azonenberg@ioc.exchange
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@ldcd you can work with it but you need to plan for it, not throw stuff down on a board and figure it out later like you usually can in xilinx land
(DIR) Post #B6h9gfmHqVL7gfzM48 by ldcd@social.treehouse.systems
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@azonenberg yup
(DIR) Post #B6h9gg2EtC6GU9S5vk by azonenberg@ioc.exchange
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@ldcd and definitely do a test bitstream before committing to pcb layout
(DIR) Post #B6h9ghbN43nRLOtfKS by ldcd@social.treehouse.systems
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@azonenberg do you know off hand if the bitstreams are encrypted by default like the microsemi FPGAs?
(DIR) Post #B6h9jywJ3mA5z7Fke0 by azonenberg@ioc.exchange
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@ldcd i have not looked at the bit files at all but the toolchain is vpr based iirc and it likely wouldn't be too hard to reverse if someone put in the work
(DIR) Post #B6h9oxBszNdG0cuXgm by ldcd@social.treehouse.systems
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@azonenberg oh really
(DIR) Post #B6h9oxNaHszQauNsvI by ldcd@social.treehouse.systems
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@azonenberg ok that is convenient...
(DIR) Post #B6h9oxYZd1mR8zWf3I by azonenberg@ioc.exchange
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@ldcd let me check in a bit but my recollection is it was forked from a lot of open tools
(DIR) Post #B6hACRwgoECU3Q0Tmi by dlharmon@chaos.social
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@azonenberg Similar feelings here.My objections to Altera now mostly apply to Xilinx as well. If/when I get to pick an FPGA for a client and it has to be high end, I'll probably let both quote parts where I would have asked for Xilinx only before.For my personal projects, the gray market KU5Ps and AU10Ps from distributors will go a long way. I don't need Kintex US+ Gen 2 for any reason.I'm evaluating Colognechip for low end with 5 Gb transceivers. Docs are lacking, probably software too.
(DIR) Post #B6hAMQeKU0JSvjB3bc by azonenberg@ioc.exchange
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@dlharmon i am sitting on a lot of sketchy ku5p and 7k160t parts plus assorted smaller that will last me a while.Trion will probably take over as my go-to for small stuff moving forward where i would have used like a spartan7.I'm hoping when the larger titanium parts hit general availability I'll be able to do stuff with more fast IO. 40x 25G serdes sounds fun
(DIR) Post #B6hAYAe9o4jwm0hCPQ by azonenberg@ioc.exchange
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@dlharmon the software has a lot of maturing to do though, i really want unified flow for transceivers
(DIR) Post #B6hAbP02tn5M9oTVIG by azonenberg@ioc.exchange
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@dlharmon the titanium hard pcie is a standard cadence ip though and i think the serdes phy likely is too
(DIR) Post #B6hmuZI8eesBpxVIJ6 by whitequark@social.treehouse.systems
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@azonenberg not even with a FOSS toolchain?
(DIR) Post #B6hmuZWfmcV0Z2Itxg by azonenberg@ioc.exchange
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@whitequark I don't like the SoC parts or their descendents (versal, zynq, su+, ku+ gen2).I will continue to use spartan/artix/kintex7 and au+/ku+ for as long as I have easy access to cheap components and a vivado 2025.1 seat and/or if the FOSS tools mature.But the newer generation products have been dead to me for a while, I was already looking at efinix because xilinx seemed to be losing their way and going all-in on acceleration and socs rather than pure play FPGAs. The licensing BS is just accelerating an already-planned migration.Efinix's stuff looks to be cheaper and also potentially larger at least than usable with free vivado (e.g. ku5p tops out at 16 transceivers matching the Ti375, but planned larger titanium parts will have up to 40x 25G transceivers)
(DIR) Post #B6hn046vUtWKrvsefo by azonenberg@ioc.exchange
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@whitequark I have disagreements with efinix about some architectural details most notably the lack of lutram, but i can make it work and ts16ff is fast enough compared to ts28hpl that I expect to be at least competitive with 7 series if not ultrascale for most stuff
(DIR) Post #B6hn9oMktH4IvvvpCa by azonenberg@ioc.exchange
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@whitequark I have concerns about the current state of the software but it will mature over time and if I get in as an early adopter hopefully i can help give them feedback to guide things
(DIR) Post #B6hnEUMQhH7YKu0exM by azonenberg@ioc.exchange
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@whitequark I would absolutely not plan a new, large design with a titanium today based on my current level of understanding of the ecosystem, I would stick with a ku+.But the only way I'm going to get that level of familiarity is to start doing test projects
(DIR) Post #B6iwtZDyc1PI2Tg7F2 by jaseg@chaos.social
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@azonenberg I’m really curious to read what your experience with them will be. I think they’re really interesting, too and I’m looking forward to seeing their upcoming 25G transceiver variants.