[HN Gopher] Imec demonstrates electrical yield for 20nm lines Hi...
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       Imec demonstrates electrical yield for 20nm lines High NA EUV
       single patterning
        
       Author : pieterr
       Score  : 15 points
       Date   : 2025-02-28 15:55 UTC (2 days ago)
        
 (HTM) web link (www.imec-int.com)
 (TXT) w3m dump (www.imec-int.com)
        
       | amelius wrote:
       | Aha, so "2nm" really means 20nm. Good to know.
        
         | jaguar1878 wrote:
         | Generally the x um or y nm of a process refers to transistor
         | dimensions (typically gate length), not metal. Minimum metal
         | pitch is still a key dimension for the ability to build useful
         | structures though, so advances like these are very useful.
        
         | staunton wrote:
         | "2nm node" means "one technology iteration after 4nm". (Well,
         | actually after 3nm, but let's not get even more into that
         | nonsense)
         | 
         | These numbers stopped having anything to do with the sizes of
         | things a long time ago.
        
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       (page generated 2025-03-02 23:00 UTC)