[HN Gopher] Hynix launches 321-layer NAND
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Hynix launches 321-layer NAND
Author : WaitWaitWha
Score : 108 points
Date : 2024-11-24 19:30 UTC (1 days ago)
(HTM) web link (www.electronicsweekly.com)
(TXT) w3m dump (www.electronicsweekly.com)
| kridsdale3 wrote:
| When I was in school studying NAND devices (2004-2010) we were
| quite apprehensive at the long term quantum stability of 4-layer
| devices.
|
| This (the past 20 years of improvement) is an incredible feat of
| engineering.
| duskwuff wrote:
| This is 321 _physical_ layers of silicon in an IC, not 321
| charge levels.
|
| QLC flash - with 16 charge levels, for four bits per cell - is
| pretty common nowadays, but that's as far as it goes so far.
| And stability is indeed a concern; modern flash devices rely
| _heavily_ on error correction.
| cma wrote:
| Memory like HBM uses stacking of silicon layers, but NAND
| flash isn't layers of silicon, it's other materials for
| capturing and holding charge with still just one silicon
| plane it's all built on top of I believe.
| hinkley wrote:
| Where's the point where you figure out how to stack chiplets
| perpendicular to a backplane instead of doing lithography 300
| times on the same chip?
| duskwuff wrote:
| That's kind of what we're doing already, although the stacking
| is parallel, not perpendicular. A lot of the innovation is in
| how the dies are tied together, cf.
| https://www.anandtech.com/show/9520/toshiba-brings-throughsi...
| creer wrote:
| This is an interesting testament to manufacturing reliability -
| that they can go to so many layers and still achieve good
| yield.
| mlyle wrote:
| As others here have pointed out -- you don't need to do
| lithography 300 times. The big breakthrough of 3D NAND is
| depositing alternating layers of films to build most of the
| layers.
|
| This is 3 stacks of >100 layers.
| fodkodrasz wrote:
| > triple level cell-based 4D memory
|
| What does 4D memory mean?
| matja wrote:
| Nothing - just marketing. It's their 2nd gen Periphery Under
| Cell (PUC) device.
| wrs wrote:
| It's marketing speak. 3D flash (stacked chips) with the control
| circuits stacked underneath instead of to the side. So it's one
| louder.
|
| https://www.tomshardware.com/news/sk_hynix-debuts-4d_nand,37...
| K0HAX wrote:
| Bigger number = more betterer
| tbrownaw wrote:
| It'd have to be something involving time... maybe have each
| cell be a delay line? Or a resonant cavity, and store multiple
| bits at different modes? Not sure how either could be made
| small enough to be worth it though...
| Animats wrote:
| Wow. What's the yield like? Are some bits bad and bypassed during
| testing?
| timschmidt wrote:
| > Are some bits bad and bypassed during testing?
|
| Always. All digital storage media depends on error correcting
| codes and sector-remapping these days.
| Neywiny wrote:
| I just want smaller SPI flash for embedded :( it's been over 10
| years since there's been improvement in that space
| duskwuff wrote:
| WLCSP-8 is pretty damn small already, at ~1.5mm square. Hard to
| get much smaller.
| Neywiny wrote:
| But they aren't high capacity. As far as I've seen, we've
| been stuck on the same XY size 512 Mb dies for over a decade.
| Even now, Infineon is claiming they have a series that'll go
| up to 4 Gb but is still at the standard 2 Gb maximum. NOR
| hasn't gotten any denser in forever.
| duskwuff wrote:
| What's the use case for a NOR flash that large? Even at 2
| Gbit, you're probably better off with something optimized
| for density like eMMC.
| Neywiny wrote:
| The use is that there's often (in my field) no space for
| an 11.5x13 eMMC. There are some that are slightly
| smaller, but as you brought up the wlcsp-8, there's
| nothing like eMMC/high capacity NAND density scaled down.
| If I had the bits/mm^2 of even NAND 5 years ago, I'd be a
| happy camper. But that's life.
| mlyle wrote:
| There's QSPI NAND parts available; they're just annoying
| to use.
|
| https://www.digikey.com/en/products/detail/winbond-
| electroni...
|
| https://www.digikey.com/en/products/detail/alliance-
| memory-i...
|
| There's also 9x8mm eMMC. The big issue with shrinking it
| further is that it tends to be a module with a separate
| controller doing lots of things to make the memory
| reasonable to use.
| Neywiny wrote:
| Yeah those are what I'm looking at, but even then we've
| been at 8Gb for years. Manufacturers only want SLC NAND
| in these for valid reasons and I guess the market isn't
| pushing for now. The 9x8 is useful but the 3.3v that eMMC
| wants means I can't power off a single cell li-ion
| without a boost. It's all a nightmare. Trust me I've
| looked for solutions, unless you know of any silver
| bullets that came out recently.
|
| And as you surely know, I usually can't boot from NAND
| (due to the aforementioned annoyance) so I'd have a boot
| flash and a storage flash and that's unideal.
|
| I'll note though that the controllers are small. You can
| RE the die size of a common eMMC<->NAND controller and
| it's much smaller than 9x8. I won't share which because I
| honestly don't remember if we got an NDA in place but
| considering they all stack dies in there anyway, I don't
| really see that as the size driver.
| bobmcnamara wrote:
| A lot of MCUs can boot from XIP QSPI/OSPI NAND. quite a
| feat of compatibility engineering - they made the NAND
| page size match QSPI transfer sizes commonly used to
| populate caches, so instead of bit level reads, the flash
| supports only cacheline level reads, which is usually
| what you need for XIP anyway.
| Neywiny wrote:
| It's too bad not every embedded device is an MCU :/
| shadowpho wrote:
| There's no money in it. Embedded doesn't pay compared to
| phones/tablets. So companies are putting their money into
| that
| Neywiny wrote:
| I'm fully aware of why there's been no improvement, it
| just sucks for me.
| xyzzy_plugh wrote:
| I left embedded when I realized everything, at least in
| my neck of the woods, was going to end up being cramming
| phone parts into things that were not phones. The writing
| has been on the wall for a while now.
|
| Even now as a consumer I can see the stagnation. It's the
| same parts year after year. Or you become a phone. You
| have my sympathy.
| badgersnake wrote:
| Are you saying that partly why every device is a "smart"
| device? Because it's cheaper to fit components with
| connectivity already built in so you might as well use
| it?
| Neywiny wrote:
| At embedded world 2024 they pushed IoT for other reasons.
| They wanted us to do it for security and updates. No more
| telling users to put a bin on a flash drive and plug it
| into a hidden port under the coffee maker or something
| idk, just be Internet connected. I wouldn't ever say it's
| cheaper materialsb (though ESP32s are very cheap) or
| upfront labor, but I'm sure it's cheaper on the support
| side for bug fixes and stuff. And then they can sell your
| data, too. Never forget that
| Neywiny wrote:
| That's what this is looking like tbh. I guess I'm just
| hoping for a miracle. Maybe chiplets will save us.
| tomcam wrote:
| Cookie permission dialog is the worst I have encountered in
| months
| randomjoe2 wrote:
| Thank god for ublock origin filters, i have all the optional
| filter lists, I never see those things. EVER.
| CoastalCoder wrote:
| I noticed that as well.
|
| I'm not sure what the rules are, but I had to disable a
| surprising number of "legitimate interests" related to
| advertising.
| StringyBob wrote:
| What does 'layer' mean in this context? I'm only familiar with
| planar style logic process nodes which have maybe up to 20 layers
| (and way more lithography steps to manufacture those layers), but
| I am completely ignorant of how the term is used for a flash
| process node.
|
| How many layers are needed for each physical cell? Is it 1,2, or
| a lot more? Is this effectively 321 physical TLC cells stacked
| vertically and some planar style logic at the bottom of the
| stack.
|
| Also, where do multiple pieces of silicon factor into this - I
| assume we might be up to 16 silicon dies deep with through-
| silicon-vias, which would mean a cross section of a package could
| actually have 5000 layers - that sounds crazy!
| brennanpeterson wrote:
| Probably done with 3 separate litho/etch layers, where they
| etch and process in groups of 110 or so.
|
| Each of those layers can have a cell, so if you have a tlc
| device at a 100nm pitch, you have a density of 321*3/(1e-4)^2
| bits/mm, or about 1e11bits/mm2.
|
| Fun reference: atomic density is 1atom/.5nm, so 1/5e-7^2, or
| 4e12/mm2 ish.
|
| Not too far away.
| StringyBob wrote:
| Amazing, I had no idea how far things had diverged between
| logic and flash since the move to 3D.
|
| https://borecraft.com/files/Comparison_Current_NAND.pdf (from
| 2019) has some of the cross-sections I was looking for - and
| that only goes up to 96 layers!
| RicoElectrico wrote:
| What's interesting is that these devices don't need 321+ litho
| steps; the vertical layers are all defined with deposition.
| Lithography step count isn't layer dependent it seems.
|
| https://youtu.be/ANHzVOiUwGI
|
| https://thememoryguy.com/3d-nands-impact-on-the-equipment-ma...
| drpixie wrote:
| Title should probably be "Hynix launches 321-layer NAND RAM".
| FabHK wrote:
| I think it might be flash memory (i.e. non-volatile, unlike
| RAM), but this must be so obvious to readers of this
| publication that it's never said explicitly.
| ksec wrote:
| If I am reading this correctly, this is still the same 1Tb per
| die but with 321 layers, meaning up to 2TB / package. The package
| should now be under 100mm2.
|
| This would hopefully bring down the price of 4TB and 8TB SSD in
| the near future.
| pajeetz wrote:
| insider info: all the top talent at Samsung left for SK Hynix
| after government stepped and forced DEI on Samsung leading to
| unqualified managers ruining Samsung's culture of innovation and
| rewarding experimentation.
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