[HN Gopher] Logik: Open-source FPGA toolchain by Zero ASIC
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       Logik: Open-source FPGA toolchain by Zero ASIC
        
       Author : jasondavies
       Score  : 20 points
       Date   : 2024-04-03 20:25 UTC (2 hours ago)
        
 (HTM) web link (github.com)
 (TXT) w3m dump (github.com)
        
       | UncleOxidant wrote:
       | Isn't it Yosys and VPR doing the heavy lifting here?
        
       | zachbee wrote:
       | This doesn't appear to support any FPGAs other than their FPGA
       | chiplet [1]. Also, like UncleOxidant said, the most complex parts
       | of this toolchain are just existing open-source tools (Yosys and
       | VPR).
       | 
       | This seems like a useful toolchain for ZeroASIC customers who are
       | using their hardware, but not for FPGA enthusiasts more broadly.
       | 
       | [1]. https://www.zeroasic.com/chiplets/fpga
        
         | sitzkrieg wrote:
         | yea this caught me too. that online digital twin is pretty
         | slick tho
        
         | hedgehog wrote:
         | I think it supports whatever SiliconCompiler supports (which is
         | both FPGA and different ASIC flows) and the EBRICK example is
         | showing how to put that design onto an ASIC or FPGA for
         | testing.
         | 
         | Edit: Here's the SiliconCompiler list:
         | https://docs.siliconcompiler.com/en/stable/user_guide/introd...
        
         | cushychicken wrote:
         | Commoditize your complements, baby.
        
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       (page generated 2024-04-03 23:00 UTC)