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Dismiss alert {{ message }} zeroasiccorp / logik Public * Notifications * Fork 1 * Star 57 * A configurable RTL to bitstream FPGA toolchain logik.readthedocs.io/en/latest/ License MIT license 57 stars 1 fork Branches Tags Activity Star Notifications * Code * Issues 0 * Pull requests 0 * Actions * Projects 0 * Security * Insights Additional navigation options * Code * Issues * Pull requests * Actions * Projects * Security * Insights zeroasiccorp/logik This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository. main BranchesTags Go to file Code Folders and files Name Name Last commit Last commit message date Latest commit History 460 Commits .github .github docs docs examples examples images images logik logik tests tests .flake8 .flake8 .gitignore .gitignore .readthedocs.yaml .readthedocs.yaml LICENSE LICENSE README.md README.md pyproject.toml pyproject.toml View all files Repository files navigation * README * MIT license Logik Regression Lint --------------------------------------------------------------------- Logik is an open source FPGA toolchain that fully automates converting RTL to bits, including synthesis, placement, routing, bitstream generation, and analysis. Users enter design sources, constraints, and compile options through a simple SiliconCompiler Python API. Once setup is complete, automated compilation can be initiated with a single line run command. logik_flow Logik supports most of the features you would expect in a commercial proprietary FPGA tool chain. Feature Status Design languages Verilog, SystemVerilog, VHDL ALU synthesis Supported RAM synthesis Supported Timing constraints (SDC) Supported Pin Constraints (PCF) Supported Bitstream generation Supported IP management Supported Remote compilation Supported Multi-clock designs In progress FPGA devices ZA Getting Started The Logik project is available through PyPi and can be installed using pip. If you want to run locally on your machine, you will need to install all of the pre-requisites or launch the Logik Docker image . python -m pip install --upgrade logik The following example illustrate some essential Logik features. For complete documentation of all options available, see the SiliconCompiler project. from siliconcompiler import Chip from logik.targets import logik_target def hello_adder(): # Create compilation object chip = Chip('adder') # Specify design sources chip.input('adder.v') # Specify pin constraints chip.input('adder.pcf') # Compiler options chip.set('option', 'quiet', True) chip.set('option', 'remote', True) # Select target fpga chip.set('fpga', 'partname', 'logik_demo') # Load target settings chip.load_target(logik_target) # Run compiler chip.run() # Display compiler results chip.summary() if __name__ == "__main__": hello_adder() This code can be run with ./adder.py -remote in the examples/adder directory, resulting in an FPGA bitstream at build/adder/job0/ convert_bitstream/0/outputs/adder.bin. To test out the generated bitstream, you can upload it to an emulated FPGA device running in the Zero ASIC Digital Twin Platform. More Examples * UMI "Hello World" * UMI FIR Filter * EBRICK demo Documentation * Logik Documentation * SiliconCompiler Documentation Installation Logik is available as wheel packages on PyPI for macOS, Windows and Linux platforms. For a Python 3.8-3.12 environment, just use pip to install. python -m pip install --upgrade logik Running natively on your local machine will require installing a number of prerequisites: * Silicon Compiler: Hardware compiler framework * Yosys: Logic synthesis * VPR: FPGA place and route * GHDL: VHDL parser * Surelog: SystemVerilog parser * FASM: FPGA assembly parser and generator Automated Ubuntu based install scripts are included for convenience within the SiliconCompiler project. Detailed instructions for installing all tools can be found in the SiliconCompiler Installation Guide. Running Docker A Docker image is provided for users who wish to avoid the installation of the pre-requisite tools. The following command starts a new container from that image and maps the local directory sc_work to the path /sc_work in the container. docker run -it -v "${PWD}/sc_work:/sc_work" ghcr.io/siliconcompiler/sc_runner:latest License MIT Issues / Bugs We use GitHub Issues for tracking requests and bugs. About A configurable RTL to bitstream FPGA toolchain logik.readthedocs.io/en/latest/ Resources Readme License MIT license Activity Custom properties Stars 57 stars Watchers 2 watching Forks 1 fork Report repository Releases 2 v0.0.2 Latest Apr 3, 2024 + 1 release Packages 0 No packages published Contributors 5 * @petergrossmann21 * @gadfort * @aolofsson * @sgherbst * @azaidy Languages * Python 100.0% Footer (c) 2024 GitHub, Inc. Footer navigation * Terms * Privacy * Security * Status * Docs * Contact * Manage cookies * Do not share my personal information You can't perform that action at this time.