[HN Gopher] What's Next for Transistors and Chiplets?
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What's Next for Transistors and Chiplets?
Author : PaulHoule
Score : 24 points
Date : 2021-10-26 14:10 UTC (8 hours ago)
(HTM) web link (semiengineering.com)
(TXT) w3m dump (semiengineering.com)
| justahuman1 wrote:
| There was a lot of new vocabulary in that for me, whats a good
| starting point for learning about modern transistors?
| dragontamer wrote:
| There's not much to say aside from "the physical shape of the
| thing matters", and that people are discovering new shapes all
| the time.
|
| I don't know if there's an easy introduction. But lemme try to
| make one really quick anyway.
|
| * Transistors themselves are just a hunk of metal, silicon
| (n-type and p-type) arranged on a platter in a particular way.
| They are physical objects, and you will do well to remember
| that. New "shapes" are invented all the time: FinFET, GAA (Gate
| All Around), and Nanosheets (brought up in this article) are
| "just" different shapes, with GAA having the best attributes so
| far.
|
| * The primary difficulty isn't really about "coming up" with a
| better shape. Everyone knew GAA would have the best attributes
| compared to others. The question is how do you __MANUFACTURE__
| the darn thing. These things are nanometers in size, its not
| very easy to make these shapes when your shapes are so
| incredibly tiny.
|
| * Transistors are an analog device, not binary/digital. You
| need an arrangement of transistors to do something: Diode-
| logic, Diode-resistor logic, Transistor-transistor logic, nMOS,
| and other arrangements have existed in the past. But... CMOS is
| the big winner from the 1970s onwards. As such, understanding
| how transistors are arranged to make your AND/OR/NAND/Flip
| flops is kinda important. That being said, I'll skip over the
| details, aside from saying "CMOS" is the status quo, and has
| the following characteristics.
|
| * In CMOS-arrangements... when the transistor is "on", you want
| less resistance. A transistor that offers 0.1 ohms of
| resistance will be better than one that offers 0.5 ohms of
| resistance (within the realm of CMOS)
|
| * When the transistor is "off", you want less leakage. The
| switch will always "leak" some electrons down the wrong path,
| its the nature of physical object. A transistor that leaks
| 1-femtoamp is better than a transistor that leaks 5-femtoamps.
| (temperature dependent: the hotter a transistor is, the more it
| leaks). Again, CMOS-specific.
|
| * Transistors take a certain amount of time to switch from 0 to
| 1, largely based off of the gate-capacitance. The lower the
| capacitance, the faster you can turn the switch on (or off).
| Being able to go from 0V to 1V in 0.1 nanosecond with 1
| femtoamp of electricity... is better than doing the same in 0.2
| nanoseconds.
|
| * Note: there is a CMOS specific tradeoff mentioned here. Maybe
| you can keep the same clockrate (5GHz / 0.2 nanoseconds) but
| use 1/2 the power (0.5 femtoamps instead of 1 femtoamp). In
| practice, this relationship is complicated as it varies with
| voltage, but there's usually a region where 2x the voltage
| leads to 2x the current and 1/2 the delay (aka 2x the clock
| rate for 4x power consumption). Or... 1/2 the voltage is 1/2
| the current and 2x the delay (aka: 1/2 speed for 1/4th power).
|
| * For CMOS, lower capacitance means faster switching (meaning
| more GHz), and lower power usage (meaning more power
| efficiency). Cutting down capacitance requires the "gate" of
| the transistor to be surrounded with more-and-more metal. When
| you increase the surface area of an object, you decrease its
| capacitance (this is a physical law that applies to your hands,
| feet, desk, etc. etc. Its how your phone knows where your
| finger is: by the amount of surface area your finger has over
| the phone's screen. As that surface area changes, your
| capacitance changes and the phone tracks your finger as it
| moves).
|
| * Capacitance / surface area applies at nano-scale objects like
| transistors. So when you made "fins" (aka: FinFET), your
| capacitance decreased, because "fins" have more surface area
| than planar (flat) transistors. FinFET became standard like 5
| to 10 years ago. To go even further: you need an "even better"
| shape (where "better" is more surface area). This is called
| "GAA", gate-all-around, where you surround the gate entirely
| (physically above, below, and left and right).
|
| * * Photolithography + magic is how these things are physically
| constructed. So called "Planar" transistors made sense and are
| relatively simple: you basically shove a bunch of chemicals
| onto the silicon, and then "reverse take a picture" of it
| (taking your film, shining light through the film, and then
| shoving that light through a lens to shrink it down. Like
| photographs in the 1980s but backwards). Because "planar
| transistors" are all flat, it was obvious how to make them.
|
| * But how do you _MAKE_ a GAA? Well, no one will tell us. They
| just show us the pictures of them successfully doing it. The
| secret sauce is in their magic processes that deposits the bits
| of metal / silicon / etc. etc. in the correct spots.
| Photolithography is an innately 2D process: built up layer-by-
| layer by successive chemicals + light emitted from a film-like
| substance. They had to make this shape from a bunch of 2D steps
| (maybe 120+ such steps) played out over the course of 2 or 3
| months.
|
| --------
|
| So TL;DR: the name of the game is:
|
| 1. Think of a shape with more surface area (less capacitance).
|
| 2. Figure out a way how to take ~120+ steps of the
| photolithography process to actually _make_ that shape in
| practice. And remember: you're mass producing 10-billion of
| these per chip, so you wanna make sure whatever process you do
| is 99.99999% reliable. A single mistake will cause the chip to
| be worthless.
|
| That's it. Really. All the "better" shapes have more surface
| area. The "older" shapes were easier to figure out on #2, while
| the "future" shapes look really hard for #2, but are obviously
| better from a surface area perspective.
| baybal2 wrote:
| The larger the area, the larger is the capacitance.
|
| Being pedantic, what matters is the field strength at the
| gate edge, and effective S term of device.
| baybal2 wrote:
| The best cycle of lectures I've ever seen in open access from
| the Centre for Nano Science and Engineering Bangalore:
|
| https://www.youtube.com/playlist?list=PLbMVogVj5nJT8RG5Q4Cps...
|
| http://www.nitttrc.edu.in/nptel/courses/video/117108047/1171...
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