Posts by infosecdj@infosec.exchange
(DIR) Post #B1PhHmjdS9gALLfmYS by infosecdj@infosec.exchange
2025-12-19T09:57:40Z
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I am always massively confused by metal-gate processes, but in general, the IC is not too complicated. From the left, we have a section of inputs wired to flip-flops, their outputs with pull-ups, then a decoder PLA matrix, terminating in a bunch of outputs. Apparently, they used the same layout for tow decoder chips, and the only difference was in how that decoder matrix was wired up.The eagle eyed among you might have noticed there are 5 flip-flops. This is because the chip takes 4 bits of the digit code plus one bit of the decimal point. Tracing the lowest-positioned FF there shows it is not connected to the PLA matrix.
(DIR) Post #B1PhHqfso33QYrwqGG by infosecdj@infosec.exchange
2025-12-19T10:02:35Z
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The PLA is the very typically organized one, with products and sums. Here is a close-up of one of the PLA outputs, with 3 product gates summed by a wired-OR. Terms come in through vertical metal, and the square openings form the gates of pMOS transistors in series. Three such gates are connected in parallel, sharing one pull-up, then driving the output transistor's gate. Really, no surprises here.
(DIR) Post #B1PhHufJy4yuwHiRwO by infosecdj@infosec.exchange
2025-12-19T10:05:37Z
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The output transistors are made slightly differently from the rest of them on this die. I am not sure why this is.
(DIR) Post #B1PhHyhEystTROe2UK by infosecdj@infosec.exchange
2025-12-19T10:08:46Z
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And that'd be it for this one! Hope you found it interesting, if so don't be shy in boosting the post! :blobcatheart:As always, my thanks goes out to my dear patrons who help offset the costs of purchasing samples and materials, and to you, dear reader. I wish you all a great end of the week.PS. You can join in here: https://www.patreon.com/NakedSilicon
(DIR) Post #B1R6VMyAjmsGV10TM8 by infosecdj@infosec.exchange
2025-12-20T09:48:57Z
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New post on my blog! Decapping with DMSO.https://dev-zzo.github.io/blarg/2025/12/19/decapping-dmso.html#electronics #reverseengineering
(DIR) Post #B2JqmdZAJmx6qPOA6K by infosecdj@infosec.exchange
2026-01-15T19:29:05Z
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As I will be travelling starting tomorrow, I declare the #nakeddiefriday today.Instead of going deeper into one particular die, this will be several of them but one-pagers.This one is HV9911 by Supertex (now owned by Microchip). Those following me have probably seen the epic struggle with restoring a diving light; this one came from the LED driver chip in the light. Entirely undamaged, as far as I can tell. Of particular interest is an array of fuses in the top right corner.#electronics #reverseengineering #icre
(DIR) Post #B2JqmezR1bYlGAgega by infosecdj@infosec.exchange
2026-01-15T19:31:40Z
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An unknown IC coming from an unlabeled 8-pin chip in a driver of a string of "fairy lights" coming form China obv. No text on the die to identify it. The exact function of this is also unknown; I suppose it is some kind of a timer to shut the lights off after some time.Notably, this is single metal layer, metal-gate CMOS process. Western companies moved on from large node metal gate processes quite a long time ago. As cheap as it gets, I suppose. The die measures 0.775mm on each side.
(DIR) Post #B2Jqmg2f75jeWTCkM4 by infosecdj@infosec.exchange
2026-01-15T19:44:11Z
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And of course I overwrote the previous post with my edits. Oh well. Yet again, here is TMP80C49 by Toshiba. It is one of the 8048 family of MCUs by intel.Note the microcode ROM on the left side and the absence of any semblance of a datapath block by it. RAM and ROM blocks on the right side.Many thanks to @RueNahcMohr for providing this sample!
(DIR) Post #B2Jqmh0ZWLepWHEajg by infosecdj@infosec.exchange
2026-01-15T19:47:17Z
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And finally, this. I have no idea what this is, except that it is Soviet and made using a metal-gate CMOS process. :-) There is two of *something* on the die, and it might be a dual JK flip-flop chip. Unfortunately, that's about as much as I know about it.
(DIR) Post #B32hfM6a7fF0F3lTkG by infosecdj@infosec.exchange
2026-02-06T08:20:39Z
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Hello! It has been a little while, but #nakeddiefriday is back in town.Today's exhibit is an old PIC1650A. Yes, one of *the* PIC series of microcontrollers. Note it was designed by General Instrument in 1980. It was fabbed in a single metal layer, metal-gate NMOS process. The image is about 4.3x3.8 mm.No full-res link as SP is still borked.#electronics #reverseengineering #icre
(DIR) Post #B32hfSQIdGZvpx2JJQ by infosecdj@infosec.exchange
2026-02-06T08:29:50Z
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We are kindly provided with a slightly yellowed block diagram of this device.One can easily identify where the program ROM is on the die; it takes a lot of space in the top left of the image. The register file is in the center left. I suppose the instruction register is the structure right below the ROM. The PC register and its incrementer is above the register file. And somewhere in there must be the ALU and decoder+control logic.
(DIR) Post #B32hfYFAzXFJtBsVo8 by infosecdj@infosec.exchange
2026-02-06T08:37:38Z
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This bit looks to be decoding at least some parts of the instruction and runs a lot of wiring to the next part. It's a PLA, of course.
(DIR) Post #B32hfeBqso9UKcMwSW by infosecdj@infosec.exchange
2026-02-06T08:39:02Z
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And this looks like the 8-bit ALU, with a 8-bit bus running on the left from the register file to the global bus, on which this unit also sits. Not much circuitry in there, somehow.
(DIR) Post #B32hfjjMHevPVz5Gsa by infosecdj@infosec.exchange
2026-02-06T08:43:55Z
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For each I/O port pin, we have 4 control signals and one data bus tap (running off to the right of the snippet here). Apparently, controls are read, write, and clear. I suppose the 4th one is global enable for the port, or similar.
(DIR) Post #B32hfph66ygK0i4YBk by infosecdj@infosec.exchange
2026-02-06T08:55:50Z
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Let's have a closer look at the ROM circuitry.The bit line multiplexer is nothing more than a 8-way NOR gate; 8 active transistors and one load. Bitlines are vertical here and are formed via diffusion.
(DIR) Post #B32hfvepwIREVR3pUu by infosecdj@infosec.exchange
2026-02-06T09:00:47Z
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But there are 8 bit lines coming in, and no selection in the mux itself. How do they choose which one is active?Turns out, they abuse the ROM structure itself and use the same transistor structures to choose the active bit line. Observe how the top 6 word lines form a binary pattern: 4, 2, 1 and their complements.
(DIR) Post #B32hg1Hf1NSrxIGPCq by infosecdj@infosec.exchange
2026-02-06T09:10:57Z
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Another interesting structure is the data bus driver. There are two instances of this exact circuit on the die. Effectively this is 8x a NOR2 with a large pull-down transistor, and one inverter (at the right) driving the common enable signal.
(DIR) Post #B32hg7CuzvEiKK5heC by infosecdj@infosec.exchange
2026-02-06T09:19:03Z
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Since we have open-drain bus drivers, the bus must be either pulled up or precharged. Chasing down that circuitry was fun! It's here. See? There are 8 L-shaped transistors, split into groups of 5 and 3. As these are actively driven, I believe the bus is precharged.
(DIR) Post #B32hgDBilHqMsLZpc8 by infosecdj@infosec.exchange
2026-02-06T09:22:34Z
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Select all MOS transistors on this picture, click Skip if there are none... :D
(DIR) Post #B32hgJP3ec4q9RrZEe by infosecdj@infosec.exchange
2026-02-06T09:26:44Z
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Well, that's about it for this Friday. Hope you enjoyed this little foray into the ancient tech. Thank you for sticking until the end!Just wanted to thank my whole one patron for supporting my work. 🖤 I do this in my free time, and would appreciate any and all support is appreciated to offset the costs of samples and supplies. If you feel you could spare some cash in this economy, I'd be most thankful. Link in the profile!Have an absolutely beautiful Friday and a fantastic end of the week!/🧵