Post AlFd1qr0pxgmLdToki by whitequark@mastodon.social
(DIR) More posts by whitequark@mastodon.social
(DIR) Post #AlEbG6h2LmZ4SZWXLs by azonenberg@ioc.exchange
2024-08-22T18:51:50Z
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Hypothesis: all short to medium range local buses will eventually converge to become PCIe, Ethernet, or both.* [S]ATA? Being replaced by NVMe over PCIe* CAN bus in cars? Being replaced by single pair Ethernet* USB4 is basically Thunderbolt which is basically PCIe* Lots of industrial RS485 etc field buses are being replaced with EthernetI suspect we're not too far from seeing a new PC monitor interface standard that encapsulates video inside Ethernet frames or PCIe TLPs the way this is headed.The unification of PCIe and Ethernet is probably further off but isn't entirely implausible.
(DIR) Post #AlEbG7HCBLUKGiRPiC by whitequark@mastodon.social
2024-08-22T18:52:19Z
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@azonenberg USB3 is already basically PCIe(that said, USB4 is not "basically Thunderbolt". it's seriously different from TBT3 and is literally the same, modulo optional feature list, as TBT4)
(DIR) Post #AlEbG80ZSdmgXRfeRE by aleksorsist@fosstodon.org
2024-08-22T19:12:06Z
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@whitequark @azonenberg holup, wasn't TBT4 just TBT3 with all the optional goodies enabled?
(DIR) Post #AlEbG8horqNYhZuBqi by ignaloidas@not.acu.lt
2024-08-22T19:14:56.947Z
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@aleksorsist@fosstodon.org @whitequark@mastodon.social @azonenberg@ioc.exchange TBT4 is USB4 with all optional goodies enabledand USB4 contains (semi-optional) TBT3 support as a legacy mode
(DIR) Post #AlEbO2ip00KWSa8uRM by azonenberg@ioc.exchange
2024-08-22T18:53:43Z
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@whitequark I'm simplifying a bit :)And USB3 is PCIe at the physical layer, but not the upper layers. USB4 is the obvious next step in further convergent evolution.
(DIR) Post #AlEbO3dtZnz3JaqUOu by whitequark@mastodon.social
2024-08-22T19:10:20Z
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@azonenberg have you looked at USB4 in depth?
(DIR) Post #AlEbO4OKn989dcZZmi by azonenberg@ioc.exchange
2024-08-22T19:10:53Z
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@whitequark No, none of my hardware supports it so I've only skimmed documentation.
(DIR) Post #AlEbO4x4hyv5NMpJw0 by whitequark@mastodon.social
2024-08-22T19:11:35Z
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@azonenberg it's actually pretty weird and a lot more complex than PCIe, without converging to it (though it does tunnel TLPs of course)
(DIR) Post #AlEbO5Tgkj0X0W5Mlk by azonenberg@ioc.exchange
2024-08-22T19:12:33Z
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@whitequark That's my point, there's a lot of extra fluff.What are the odds that USB5 will be like "screw this, do a quick negotiation via the CC pins then just shove pcie over the superspeed pairs"?
(DIR) Post #AlEbO6FXsnHxOwTaMa by ignaloidas@not.acu.lt
2024-08-22T19:16:22.850Z
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@azonenberg@ioc.exchange @whitequark@mastodon.social You don't want to tunnel DisplayPort packets with the same guarantees as PCIe packetsUSB4 is pretty complex and weird because of these.
(DIR) Post #AlEbrAw3Xa0gKcDynw by aleksorsist@fosstodon.org
2024-08-22T19:18:01Z
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@ignaloidas @whitequark @azonenberg Sure, but what's the actual difference between TBT3 and TBT4 if not just the spec requirements I mentioned?
(DIR) Post #AlEbrBgUkv9medx4Bk by ignaloidas@not.acu.lt
2024-08-22T19:21:35.074Z
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@aleksorsist@fosstodon.org @whitequark@mastodon.social @azonenberg@ioc.exchange the fact that the protocols are so completely differentAs I said, it's just USB4, plus Intel's marketing on optional features. You'd get the exact same on AMD based systems sans Intel marketing.And USB4 is really, really different from "PCIe with some considerations for cables" that is TBT3 protocol.
(DIR) Post #AlEdPW5TVLb1jVZLFI by whitequark@mastodon.social
2024-08-22T19:12:54Z
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@aleksorsist @azonenberg no(which goodies would that even be?)
(DIR) Post #AlEdPWevNXx7VS9eV6 by aleksorsist@fosstodon.org
2024-08-22T19:16:53Z
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@whitequark @azonenberg Enforced minimum transfer speed, wake from sleep required, dma protection required. All things you could do on TBT3 but now there's no ambiguity.
(DIR) Post #AlEdPXSYP1eRzNNHrE by whitequark@mastodon.social
2024-08-22T19:19:16Z
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@aleksorsist @azonenberg the wire protocol is pretty different, so no, not really...
(DIR) Post #AlEdPYCddgVyIIw5gm by aleksorsist@fosstodon.org
2024-08-22T19:22:18Z
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@whitequark @azonenberg so what changed? Everything I've seen online about it is either what I just said, or vaguely pointing out that it is different. I don't have access to any non-public data and because of ThunderScope I'd rather not cross that line and get turbo sued by Intel
(DIR) Post #AlEdPYljXCaU39M7OK by whitequark@mastodon.social
2024-08-22T19:25:26Z
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@aleksorsist @azonenberg then I don't think I should be telling you anything about TBT3?like, beyond "the wire protocol is completely incompatible" (since the details of the TBT3 wire protocol are not public at all)I did point out that it runs at a different rate and has a different packet format and no MPLS-like structure, I don't know what more are you asking if you can't touch TBT3
(DIR) Post #AlEdPZOjCDmO05bGAi by ignaloidas@not.acu.lt
2024-08-22T19:39:03.076Z
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@whitequark@mastodon.social @aleksorsist@fosstodon.org @azonenberg@ioc.exchange (since the details of the TBT3 wire protocol are not public at all)they mostly are, in the USB4 spec, section 13, Interoperability with ThunderboltTM 3 (TBT3) SystemsIntel released them specifically for compatibility. It's not the original spec variant, but it seems to be just enough to run TBT3 once you have the rest of USB4 up and running
(DIR) Post #AlEdavOjjy5hPz1CvQ by aleksorsist@fosstodon.org
2024-08-22T19:30:22Z
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@whitequark @azonenberg Something something plausible deniability, for all i know you measured it lol. You said the line rates were in a public doc, have a link? I'm mostly just curious since ThunderScope uses TBT3 adaptors rn - works identically with TBT4 ones though
(DIR) Post #AlEdaw4vD7ppWoktg8 by ignaloidas@not.acu.lt
2024-08-22T19:41:07.819Z
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@aleksorsist@fosstodon.org @whitequark@mastodon.social @azonenberg@ioc.exchange here's an excerpt with line rates from USB4 spec, about as primary source as you can get
(DIR) Post #AlEdldFpXRVIKdxTEG by whitequark@mastodon.social
2024-08-22T19:42:02Z
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@ignaloidas @azonenberg @aleksorsist oh, they did? back when I first looked at them, that part was just a bunch of opaque registers that gave you no useful information. I'd have to take another look
(DIR) Post #AlEdleAC9saf9SKU5I by ignaloidas@not.acu.lt
2024-08-22T19:43:04.115Z
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@whitequark@mastodon.social @azonenberg@ioc.exchange @aleksorsist@fosstodon.org I mean it's still mostly that, it's just that as far as I can tell, PCIe tunneling on USB4 is pretty similar to how TBT3 does things.
(DIR) Post #AlFd1oPHw4K8l4UeGG by timonsku@mastodon.social
2024-08-22T19:09:36Z
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@azonenberg DisplayPort is already a packet based interface and is in many regards very similar to PCIe signaling wise.At least on the PHY side of things everything will or is already looking like PCIe. On the protocol layer I think we will still see some differences for special purpose stuff like displays but yea, we are very close to that reality except that USB2 will never die lol
(DIR) Post #AlFd1p5pNuLqt0OcZE by funkylab@mastodon.social
2024-08-22T19:17:36Z
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@timonsku @azonenberg and imho, that's excellent. It's nice that we can unify so many things, but USB low/full speed is exactly the thing you'd want to build robust low-speed peripheral networks. A mouse really doesn't need to support BAR or be safe to map using an IOMMU, and neither does a thermal sensor or blinkenlights.
(DIR) Post #AlFd1px0CCszXvH5Rw by timonsku@mastodon.social
2024-08-22T19:38:19Z
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@funkylab @azonenberg yea USB as a protocol will and should not go away. USB2 just has an absolute awful PHY that we really do not need. Doing USB2 protocol layer over USB3 PHY at the same speed classes would have been nice but it didn't happen.
(DIR) Post #AlFd1qL6kaAUkgYL1U by azonenberg@ioc.exchange
2024-08-22T19:39:02Z
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@timonsku @funkylab The lack of transaction translator support for running multiple USB2 devices on a 5 Gbps upstream is IMO the single biggest problem in the USB3 spec.
(DIR) Post #AlFd1qr0pxgmLdToki by whitequark@mastodon.social
2024-08-22T21:28:47Z
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@azonenberg @timonsku @funkylab have you tried to implement a USB2 hub with TTs?
(DIR) Post #AlFd1rjbYzMF4x1PqS by azonenberg@ioc.exchange
2024-08-22T21:29:52Z
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@whitequark @timonsku @funkylab No. If it's difficult to impossible because of the previous gen protocol being poorly designed, that does not change my overall opinion (that this not being practical is a bug in the spec... just a bug in the 2.0 spec rather than the 3.0)
(DIR) Post #AlFd1sLXHxhOyalhy4 by whitequark@mastodon.social
2024-08-22T21:32:19Z
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@azonenberg @timonsku @funkylab that's a strange position coming from a hardware person like you; even as I don't like USB at all (whichever version) I have to acknowledge the difference between "poorly" and "to requirements that no longer hold" (bearing in mind that it's a combination of the two)
(DIR) Post #AlFd1t86NOXzPDUUfQ by azonenberg@ioc.exchange
2024-08-22T21:33:32Z
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@whitequark @timonsku @funkylab Which requirements, exactly?Everything about the 2.x protocol seems to be a pain, but from what I've looked at I couldn't see any fundamental reason why you couldn't encapsulate 2.x traffic inside superspeed packets.
(DIR) Post #AlFd1tsBc3PVi93IUy by equinox@chaos.social
2024-08-23T00:42:50Z
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@azonenberg @whitequark @timonsku @funkylab or just define THCI, for an USB 2.0 controller attached via USB 3.0. Like Thunderbolt does it for providing USB ports down the line…
(DIR) Post #AlFd1tvjOsFJt8i81Y by azonenberg@ioc.exchange
2024-08-22T21:37:44Z
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@whitequark @timonsku @funkylab (the half duplex nature of the 1.x / 2.x PHY was another huge thing I hated about it... a six wire full duplex cable/connector wouldn't have been THAT much more expensive or bulky)
(DIR) Post #AlFd1ugAcDOQDARDPM by whitequark@mastodon.social
2024-08-23T00:43:53Z
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@equinox @azonenberg @timonsku @funkylab (I think that's more or less what USB4 does? but now you have to deal with USB4, which is an even worse can of worms)
(DIR) Post #AlFd1vJAHEaKA6gMBk by ignaloidas@not.acu.lt
2024-08-23T07:09:27.767Z
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@whitequark@mastodon.social @equinox@chaos.social @azonenberg@ioc.exchange @timonsku@mastodon.social @funkylab@mastodon.social no it doesn'tThunderbolt has the benefit of guaranteed PCIe, and as such just throwing a PCIe to USB2 host adapter is dead easy. However, USB4 does not have this luxury, as it does not strictly require host to support tunneling PCIe through it (even though every host so far does, I think this was left so you wouldn't need phones to support PCIe, but no phone yet has USB4 AFAIK). So realistically, you'd either need to tunnel USB2 itself in USB4, which I'm not sure is a great idea, or implement USB3 to USB2 TT (and we know that's not happening).Maybe with USB5 if it ever happens. Maybe.