Post AkpMS2XHHFiKmDC1AW by JF@mastodon.codingfield.com
 (DIR) More posts by JF@mastodon.codingfield.com
 (DIR) Post #AkpMS2XHHFiKmDC1AW by JF@mastodon.codingfield.com
       2024-08-10T15:01:12Z
       
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       What's going on with those multi-ISA MCU (like the CV1800B, the SG2000 and the new RP2350)? Don't get me wrong, those are nice chips that are very funny to play with but... what's the use-case?Are those chips only targeted to hackers and tinkerers or are there actual use-cases for those chips with 2 (exclusive) main cores with different ISA (ARM/RISC-V) ?
       
 (DIR) Post #AkpPtgvjV1ojjsVaIC by deshipu@fosstodon.org
       2024-08-10T15:39:48Z
       
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       @JF In case of the Raspberry Pi, it looks like it's their way of promoting and exploring the architecture, while at the same time minimizing their risk. If they made a chip that is entirely RISC-V, only a few enthusiasts would buy it. This way, they are putting RISC-V cores in the hands of people who would not normally get out of their way to try them, but might as well since they come for free with a chip they are using anyways. It's an investment to get rid of the licensing fees in the future.
       
 (DIR) Post #AkpQU1V2V49rxWLZyq by piggo@piggo.space
       2024-08-10T15:26:48.214003Z
       
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       @JF is riscv  a low power coprocessor? Maybe so they don't have to pay licensing
       
 (DIR) Post #AkpQU2itx0qBknqAE4 by JF@mastodon.codingfield.com
       2024-08-10T15:46:23Z
       
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       @piggo In the case of the SG2000 and RP2350, you can select if you want the ARM core OR the RISC-V core to "boot" as the main core (the other one is disabled).The SG2000 also have another RISC-V core and a 8051 core as coprocessor but yeah, it still allow to boot either on the ARM or RISC-V "big" core.
       
 (DIR) Post #AkpQozRnKG03fupLPM by JF@mastodon.codingfield.com
       2024-08-10T15:50:11Z
       
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       @deshipu Mhm interesting! So the idea is to provide the very same die to users who want ARM AND to those who want RISC-V. But the goal is not necessarily to build an application that  can run on both of the cores at the same time.
       
 (DIR) Post #AkpSVy6EJRHftvnWyG by deshipu@fosstodon.org
       2024-08-10T16:09:09Z
       
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       @JF Yeah, making a new chip is a very expensive endeavor, but adding an extra core or two to a chip you are already making is considerably less expensive. So basically the Cortex-M33 cores are paying for the Hazard3 cores here. You can select any two of the four cores at boot time, so in theory you could have one ARM and one RISC-V core running, but it's unclear what advantages that would give you in practical terms.
       
 (DIR) Post #AkpW3fYC5E0q54dh7w by shironeko@fedi.tesaguri.club
       2024-08-10T16:48:54.790569Z
       
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       @JF maybe it's to aid transition? you can "upgrade" to riscv without a field replacement