Post AklpLhuJBHP36DSSsC by ShadowInTheVoid@topspicy.social
(DIR) More posts by ShadowInTheVoid@topspicy.social
(DIR) Post #AkligPp0uxprPVuQ7M by foone@digipres.club
2024-08-08T20:38:38Z
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That new pico is neat. A chip that can change architectures? And even, technically, run as two heterogeneous cores?Neat! Can you add x86 to the pico3? Thanks.
(DIR) Post #AklirxqWkwTs7Y7jsm by foone@digipres.club
2024-08-08T20:40:12Z
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I do really like the idea of a chip that boots up, checks to see what CPU architecture its flash code is in, then reboots to support that architecture instead
(DIR) Post #Aklis0CE1F1dPQI5yq by foone@digipres.club
2024-08-08T20:40:44Z
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Like I'm imagining sticking an 80486 in a Mac and it notices the firmware is powerpc so it reboots into being a powerpc chip
(DIR) Post #Akljwwa8z411bNOnQW by foo@fosstodon.org
2024-08-08T20:52:25Z
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@foone And yet Transmeta never added SPARC to the Crusoe like they said they would...
(DIR) Post #Aklk7ycbjyPJ75oQEK by hakirsch@furries.club
2024-08-08T20:55:34Z
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@foone isn't this slightly kind of but not really like the Transmeta Crusoe?
(DIR) Post #AklkFuIPhuak0w9F3o by foone@digipres.club
2024-08-08T20:56:14Z
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@munin just make the x86 bigender too!
(DIR) Post #AklkMsqjU2jLYTWkWu by foone@digipres.club
2024-08-08T20:57:34Z
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@MuseumJoe the datasheet, under 3.9.2. Mixed Architecture Combinations, says you can do mixed arch setups, just that they're not sure why you would want to
(DIR) Post #AklkTzagomvqUQPfFY by foone@digipres.club
2024-08-08T20:58:15Z
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@hakirsch nah! They're not doing code morphing or anything: the chip has four cores (two of each arch) and at boot it picks which two to turn on
(DIR) Post #Aklmmz1pKh4E9kI0oq by sphereinabox@hachyderm.io
2024-08-08T21:36:37Z
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@foone not 8051?
(DIR) Post #AklmuRnel9q3PsDjVo by Nentuaby@wandering.shop
2024-08-08T21:37:48Z
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@foone @MuseumJoe Presumably because it's still not a capital crime for upstream vendors to ship opaque blobs.
(DIR) Post #Akln2A6IRulgq6cMvg by markjustmark@aus.social
2024-08-08T21:39:23Z
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@foone @munin big-ender or bi-gender ?
(DIR) Post #AklnjPRFIbWqrS2SIa by Rainne@mastodon.social
2024-08-08T21:45:34Z
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@foone When you inevitably construct firmware that reads as valid for any architecture the CPU supports, what will it do?
(DIR) Post #Aklo5qHQBRB6Tn8kbY by tedmielczarek@mastodon.social
2024-08-08T21:46:59Z
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@foone is transmeta still a thing?
(DIR) Post #AkloQbDLOPd5pq8AQi by foone@digipres.club
2024-08-08T21:47:09Z
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@markjustmark @munin it can be both, if you're a robot girl!
(DIR) Post #AklodJwcuc4E2TNSPg by foone@digipres.club
2024-08-08T21:48:04Z
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@tedmielczarek nope! defunct since 2009
(DIR) Post #AklomY6JeHgqYAJGvg by foone@digipres.club
2024-08-08T21:51:25Z
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to explain something for anyone who hasn't read the RP2350 datasheet:It doesn't do any code-morphing or translation or anything. The CPU is designed with 4 cores, but two slots for connecting to the rest of the CPU fabric. So at boot it selects which two cores to power on. So it can be 2xARM or 2xRISCV or (technically!) 1xARM and 1xRISCV. There's no fancy stuff where there's a single CPU arch that can run multiple things: it's just multiple heterogynous cores.
(DIR) Post #Aklp6PGqBmY0xHhYjw by foone@digipres.club
2024-08-08T22:02:19Z
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@rudi yeah, sadly.
(DIR) Post #AklpDdEseZAoIwEJsm by foone@digipres.club
2024-08-08T22:03:24Z
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@Gaelan I really don't know. I guess some people are looking to try risc-v? and this lets them do that without needing to buy a risc-v-only board.
(DIR) Post #AklpLhuJBHP36DSSsC by ShadowInTheVoid@topspicy.social
2024-08-08T22:03:41Z
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@foone id rather see 680x0 and Z80 if we can
(DIR) Post #AklpS9mgRoydIOy1WS by henryk@chaos.social
2024-08-08T22:04:04Z
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@foone Ok. But, why?
(DIR) Post #AklqGNL2KP97oPyulE by zrail@hachyderm.io
2024-08-08T22:15:26Z
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@foone not just at boot! Boot selects core 0 but you can pick what arch to start for core 1 at runtime. You have to ship two binaries of course, and it seems like the tooling isn't quite there yet. But it's possible.
(DIR) Post #Aklqv63HVGFq4Y5t8y by keisisqrl@mastodon.eternalaugust.com
2024-08-08T22:22:27Z
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@foone BAFFLING move, but neat
(DIR) Post #AklslfzhDSSWYd3Kq0 by fsphil@mastodon.social
2024-08-08T22:43:36Z
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@foone Reminds me a little of the Commodore 128 with it's selectable 8502 / Z80.
(DIR) Post #AkltxnzbP5FMnGM9mC by HorayNarea@chaos.social
2024-08-08T22:54:03Z
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@foone Pico3 "Transmeta Edition"? 🥺
(DIR) Post #AkluxGyeFnugLuDhtA by LovesTha@floss.social
2024-08-08T23:05:36Z
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@zrail @foone can core 1 be rebooted into the other arch while keeping core 0 running? (not something I'd normally expect to work, but this sounds like a device that might want to be able to do that)
(DIR) Post #AkluxHnLDKSkt7wBu4 by foone@digipres.club
2024-08-08T23:07:52Z
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@LovesTha @zrail I don't think so. I think you set the arch bits to select which cores you want, and then reboot the whole CPU
(DIR) Post #AklwyuSl8H5R0rDEhs by jeremy_list@hachyderm.io
2024-08-08T23:30:08Z
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@foone why add x86 when you can add 6502?
(DIR) Post #Aklx4GCbjVR3suD1cm by thelobdegg@mastodon.social
2024-08-08T23:31:06Z
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@foone Is there a reason why you're only allowed to activate 2 of the 4 cores? Is it like a timing thing?
(DIR) Post #Akly2fknrV0CVS0iMS by jlargentaye@mas.to
2024-08-08T23:42:48Z
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@foone it’s weird that they include 2 cores in the die that *cannot be used* (i.e. you can only use ARM XOR RISC-V)I’m so used to designs that maximize layout usage that wasting space on useless extra hardware seems heretical.I guess whichever node they’re fabbing at is cheap enough, that the die space isn’t critical.
(DIR) Post #Akm2ajZoYTHA1bMsAy by LovesTha@floss.social
2024-08-09T00:33:33Z
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@foone @zrail :(
(DIR) Post #Akm2jSav40c1xh2tVY by grishka@friends.grishka.me
2024-08-09T00:35:19Z
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Foone🏳️⚧️, idk but that feels kinda wasteful? But then also looking at how comparatively little die area an actual CPU core usually occupies on modern chips... 🤔
(DIR) Post #Akm2yHIbLH0tH0Xk2q by grishka@friends.grishka.me
2024-08-09T00:37:37Z
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Foone🏳️⚧️, so maybe an even more versatile chip. Like, a gate array. That can be programmed in the field.
(DIR) Post #Akm3506dfCDbyf9ZnE by foone@digipres.club
2024-08-09T00:38:33Z
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@grishka yeah I think that's the real reason they did this: they had free die space so why not?
(DIR) Post #AkmXT6GBQqgide1dWC by pl@social.hackerspace.pl
2024-08-09T06:19:09Z
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@foone back around 2010 a friend of mine brought a complete IBM PC compatible on a stick, an SoC with IIRC 486 compatible, few megabytes of memory (enough to boot Linux), some small flash, USB1.1 host/device, serial port, and some flash memory. Most of it in one chip, maybe a tiny bit bigger than QFN80 version of RP2350. We used it to enhance our 68hc11 robotics project (MIT Handyboard).These days it would probably fit in only slightly bigger RP2350...
(DIR) Post #AkmciPmpc9s1JVQ048 by hex@meow.lgbt
2024-08-09T07:18:33Z
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@foone consider the following: triple-mode model that can switch between x86, RISC-V, and PowerPC, able to run in any triple-core combination of those three.