Post AXWSrAsRyKuK19zVnU by ignaloidas@not.acu.lt
(DIR) More posts by ignaloidas@not.acu.lt
(DIR) Post #AXWRvHn2753Mf2r0Zk by niconiconi@mk.absturztau.be
2023-07-09T15:43:36.944Z
1 likes, 0 repeats
USB 3.0 signaling protocol be like...
(DIR) Post #AXWRvIgKnTHzQYjAm0 by ignaloidas@not.acu.lt
2023-07-09T15:45:45.343Z
0 likes, 0 repeats
@niconiconi@mk.absturztau.be well, it's about 1.6x faster/0.625x slower clockspeedthough to be fair, there's not much to invent when you're doing high speed serial signaling
(DIR) Post #AXWSrAFoI0005JueZM by niconiconi@mk.absturztau.be
2023-07-09T15:54:51.614Z
1 likes, 0 repeats
@ignaloidas@not.acu.lt I really need to finalize and release my ultra-low-cost USB 3 extension board project that runs a USB signal directly into 10 GbE SFP+ modules... The PCB costs $10, the best bang for the buck if you can find cheap SFP+ modules retired from servers.
(DIR) Post #AXWSrAsRyKuK19zVnU by ignaloidas@not.acu.lt
2023-07-09T15:56:10.755Z
0 likes, 0 repeats
@niconiconi@mk.absturztau.be hah, that does sound pretty neatthough of course that probably doesn't handle 2.0 signaling
(DIR) Post #AXWXPuLxncwMinc5w0 by wi24rd@misskey.io
2023-07-09T16:37:11.781Z
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@niconiconi@mk.absturztau.be really? Also 3.1 and later?
(DIR) Post #AXWXPutzl6A8QLXGym by niconiconi@mk.absturztau.be
2023-07-09T16:44:58.958Z
1 likes, 0 repeats
@wi24rd@misskey.io If carefully designed, you can basically reuse basically same transceiver PHY for PCIe, DisplayPort, SATA and USB 4 all at the same time. It's what Intel did under the PIPE standard. https://www.intel.com/content/dam/www/public/us/en/documents/white-papers/phy-interface-pci-express-sata-usb30-architectures-3-1.pdf
(DIR) Post #AXWY7ymggbcjCp80sy by ignaloidas@not.acu.lt
2023-07-09T16:55:15.023Z
0 likes, 0 repeats
@niconiconi@mk.absturztau.be @wi24rd@misskey.io Well, not so sure about the highest 80Gbps speeds of USB4, since that uses PAM3, and that changes the transceiver design quite a bit.