Post AXFqdnBMFbkigSKQym by aer@freeradical.zone
 (DIR) More posts by aer@freeradical.zone
 (DIR) Post #AXFqdnBMFbkigSKQym by aer@freeradical.zone
       2023-07-01T12:45:42Z
       
       0 likes, 1 repeats
       
       One of the neat things we do in CPU design is basically delete x86 zeroing idioms from the instruction stream.A=A xor A, things of that nature. Shortcuts to set a register to zero.We just detect them, delete the instruction, add an entry to the retire queue (so dependent ops don't get messed up), then set all the select lines to an ALU input mux to zero, causing the output to become zero. It's like a free zero register resulting from a quirk of how muxes work.
       
 (DIR) Post #AXFqdqGmlssQG9tJM8 by aer@freeradical.zone
       2023-07-01T12:47:14Z
       
       0 likes, 0 repeats
       
       I work on the L1 data cache, so I don't get a ton of exposure to how the execution unit works, and barely any exposure to the decode/frontend units, but sometimes I learn things like this and it's like gaining eldritch knowledge