Post AWiDvrxWRaXJRNBgp6 by boyter@honk.boyter.org
(DIR) More posts by boyter@honk.boyter.org
(DIR) Post #AWhuIsbNOQbF72gCJ6 by boyter@honk.boyter.org
2023-06-15T06:32:49Z
3 likes, 3 repeats
With the new AMD server CPU's having 1 GB of Level 3 cache its a countdown to a Linux flavor named CacheOS where the OS + userspace runs in L3 cache, and RAM is the swapfile.
(DIR) Post #AWhubS4EGwaEJq1zZw by gabriel@mk.gabe.rocks
2023-06-15T06:36:48.597Z
1 likes, 0 repeats
@boyter@honk.boyter.orgMore bloat will be demanded.Everything will be ported to webassembly so that systemd can run as an electron app.
(DIR) Post #AWhupsW8jC6mPHxuCW by colinsmatt11@gleasonator.com
2023-06-15T06:39:26.021542Z
0 likes, 0 repeats
@boyter You can run debian on it after a bit of stripping.
(DIR) Post #AWhyPZabhw5dtBbwwa by m0xee@social.librem.one
2023-06-15T07:19:31Z
1 likes, 0 repeats
@gabriel @boyter And all other software would run in its own containerized instance of an OS… Wait, we already have that 😩
(DIR) Post #AWi3soteNHlNX3HeEq by newt@stereophonic.space
2023-06-15T08:20:31.809797Z
1 likes, 0 repeats
@boyter I mean, this has been a reality for years now. I remember seeing a Linux distro that operated out of L3 cache just like you describe.
(DIR) Post #AWiDm6UtXJ9ldO8mhs by boyter@honk.boyter.org
2023-06-15T10:11:37Z
0 likes, 0 repeats
@newt I really hope it’s getting closer to being a reality that’s the norm. I’d love the speed.
(DIR) Post #AWiDrBl5P2H9Op8fB2 by wolf480pl@mstdn.io
2023-06-15T07:05:51Z
0 likes, 0 repeats
@boyter that would only make sense if Linux had a much better idea than hardware about what data should be in last-level cache. The idea would need to be so much better as to outweight the impact on L1/L2 and CPU time of memcpying unused data between cache and DRAM
(DIR) Post #AWiDrCQYupS7TSXmpE by boyter@honk.boyter.org
2023-06-15T10:12:34Z
0 likes, 0 repeats
@wolf480pl Totally, but I’m sure someone out there is working on it now that his is about to be a reality.
(DIR) Post #AWiDvrxWRaXJRNBgp6 by boyter@honk.boyter.org
2023-06-15T10:13:25Z
1 likes, 0 repeats
@colinsmatt11 That’s what I hope becomes the norm. I imagine it would feel zippy as heck.
(DIR) Post #AWiDz5PksEMW2YvXxQ by boyter@honk.boyter.org
2023-06-15T10:14:00Z
1 likes, 0 repeats
@gabriel ye gods. Please don’t give people ideas like that.
(DIR) Post #AWiE1SWvtuRsJOPr3Q by boyter@honk.boyter.org
2023-06-15T10:14:25Z
0 likes, 0 repeats
@m0xee hah!
(DIR) Post #AWiIhuGxXri4KfRNIG by newt@stereophonic.space
2023-06-15T11:06:30.581910Z
0 likes, 0 repeats
@boyter you won’t have it. Without L3 cache, the CPU will be much much slower.
(DIR) Post #AWiInzWEx4wKLEUOx6 by thatbrickster@shitposter.club
2023-06-15T11:08:01.221146Z
2 likes, 1 repeats
@newt Can't wait for seL4 to run entirely in L4 cache.@boyter
(DIR) Post #AWiQUjP9RK7EUkV6a8 by newt@stereophonic.space
2023-06-15T12:33:47.854620Z
0 likes, 0 repeats
@thatbrickster @boyter hahaha if you have L4 cache, I don't envy you!
(DIR) Post #AWiQzhZ8KKvllhwBhg by thatbrickster@shitposter.club
2023-06-15T12:39:46.457179Z
1 likes, 0 repeats
@newt I hear 14th gen Intel CPUs will have it. Never too early to set the trend.@boyter
(DIR) Post #AWj28knlMUMGiNxa5Y by boyter@honk.boyter.org
2023-06-15T19:35:58Z
0 likes, 0 repeats
@newt My guess would be with some smart usage you could still have some left over for normal operation.
(DIR) Post #AWj2DONq8gkMdO2wfQ by boyter@honk.boyter.org
2023-06-15T19:36:50Z
0 likes, 0 repeats
@thatbrickster I heard that too. A response to the 3d amd cache I suspect. All I know is that CPU’s are exciting again.
(DIR) Post #AWj2Vwy6IB3t6rr8qW by newt@stereophonic.space
2023-06-15T19:39:45.710760Z
0 likes, 0 repeats
@boyter sorry, no.X86 CPUs have a mode where you can use L3 cache as RAM, it is used during early initialisation when RAM isn't yet available. But it's all or nothing. You can't just use a part of your cache for main memory, leaving the rest of it operating as cache.The way I saw it used (other than the above) was in some paranoidly secure system fortified against cold boot attacks, since you can't easily freeze the CPU, put it onto another board, and read the cache contents. The system supported regular RAM as well, but it was encrypted, with keys never physically leaving the CPU.
(DIR) Post #AWjK6PSXXUtv7Q45dQ by boyter@honk.boyter.org
2023-06-15T22:57:15Z
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@newt Yep I get that. What I am saying is that we are rapidly getting to the point where using on chip cache as your main memory is rapidly approaching.This raises some interesting ideas where you literally have enough cache to run the OS and all your user space applications in cache, and then treat actual RAM as swap.This of course requires a huge change to the way things actually work, BUT think about the benefits. I would be prepared to trade a fair bit to work on that cache and get the benefits of it.
(DIR) Post #AWjKCgJnlq338xy6WO by ringo@talk-here.com
2023-06-15T22:58:20.715754Z
1 likes, 0 repeats
@boyter @newt or in the old days if a drive was on its way out you could put the OS and kernel in ram and just run it that way.this is similar.
(DIR) Post #AWjKbZdfk3lZfQ8GDQ by newt@stereophonic.space
2023-06-15T23:02:27.991507Z
0 likes, 0 repeats
@boyter this has been possible for like 20 years now, give or take. Itanium CPUs had enormous caches for their time, albeit more out of necessity.Not sure if losing CPU cache would have any benefits except some security. It would certainly hinder performance a lot.
(DIR) Post #AWjKpt7S6xcy8dt4HQ by boyter@honk.boyter.org
2023-06-15T23:05:28Z
0 likes, 0 repeats
@newt What I am suggesting is not removing the cache, but that we have enough to keep most of its benefits while keeping your system mostly in it.Also long term, 1 GB today, where will we be in 10 years.
(DIR) Post #AWjKvK27TObL3gz4Fs by a1ba@suya.place
2023-06-15T23:06:28.444642Z
0 likes, 0 repeats
@thatbrickster @boyter @newt some old Intel CPUs already had L4 caches which wasn't that great except games as far as I know
(DIR) Post #AWjLeyb3VQ5DtZ5vc0 by newt@stereophonic.space
2023-06-15T23:14:23.353266Z
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@boyter yeah, I understand that. My point is, if you start to manage this piece of memory explicitly (as oppose to transparent cache), then it stops being a cache.If I understand you correctly, what you want is having RAM in your SoC. Which has long since happened in many embedded systems.
(DIR) Post #AWjNJlSZLx1Iyl8dg8 by boyter@honk.boyter.org
2023-06-15T23:33:16Z
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@newt Nah. More just a random thought. I don't see anything happening anytime soon for this.However I do think its going to rapidly get to the point where running without RAM (or indeed using it only as swap) is going to be possible for a lot of users, and probably sooner than we think.Going to require some rethinking about how we design and build things though.The potential gains seem great though!
(DIR) Post #AWjn2lUEb73kwoTJeC by ignaloidas@not.acu.lt
2023-06-16T04:21:32.926Z
0 likes, 0 repeats
@wolf480pl@mstdn.io @boyter@honk.boyter.org TCM should be the standard, and cache only as a mode on topMy rough calculations also show that you'd get like 5% size increase as well as some latency improvements with things operating in TCM mode because of the extra data you need to store for cacheof course to utilize them, software would have to be written for it, but it's nothing that couldn't be done.
(DIR) Post #AWk38vyq5t7QUskbHU by newt@stereophonic.space
2023-06-16T07:21:35.173413Z
0 likes, 0 repeats
@boyter what would those benefits be?
(DIR) Post #AWkL4uzJdjDxR6CyDA by boyter@honk.boyter.org
2023-06-16T10:42:50Z
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@ignaloidas I’m all for seeing it happen.
(DIR) Post #AWkLDtVSW9IjRnWUVM by boyter@honk.boyter.org
2023-06-16T10:44:31Z
0 likes, 0 repeats
@newt the usual, improved latency, faster more responsive software. I’d fully expect us to squander it over time but it could be amazing.
(DIR) Post #AWkUChK5EGZOxVhrd2 by newt@stereophonic.space
2023-06-16T12:24:39.530915Z
0 likes, 0 repeats
@boyter yeah, this is just what Apple did by soldering RAM right next to their SoCs.Agree with you here. Having _some_ RAM soldered right next to the die and more but slower RAM in expansion slots would totally rock.
(DIR) Post #AWkV22viecxSjynMhc by newt@stereophonic.space
2023-06-16T12:34:01.983874Z
0 likes, 0 repeats
@boyter although, let's face it. The reason why our software these days seems unbearably slow has nothing to do with lacking hardware performance. And everything to do with said software having poorly architected and developed. The very fact that a glorified document viewer is the single most complex piece of software that probably chugs on most of resources here is just horrifying.