Post ATy46wZ92Dygf8k0R6 by gpshead@infosec.exchange
 (DIR) More posts by gpshead@infosec.exchange
 (DIR) Post #ATxKL2Ew8jP0QI4PxI by mjg59@nondeterministic.computer
       2023-03-24T23:28:27Z
       
       0 likes, 0 repeats
       
       I've shitpost about this before (https://twitter.com/mjg59/status/1495281551931854849), but: is there any reason you couldn't bring up modern x86 purely using Cache-as-RAM and never initialising the memory controller? I assume DMA would be an issue, but you ought to be able to bitbang some amount of graphics hardware into functionality.
       
 (DIR) Post #ATxNRMfpNdwdOgMGKu by est@social.emily.news
       2023-03-25T00:03:03Z
       
       0 likes, 0 repeats
       
       @mjg59 i have wondered about this before.maybe you could implement some kinda DMA stub in the kernel. like some kinda..."mutant DMA"
       
 (DIR) Post #ATxNkwWEKhba4TCjvE by mjg59@nondeterministic.computer
       2023-03-25T00:06:42Z
       
       0 likes, 0 repeats
       
       @est Emily. No.
       
 (DIR) Post #ATxNs6muYElVwmQKZ6 by cr8@mastodon.social
       2023-03-25T00:07:38Z
       
       0 likes, 0 repeats
       
       @mjg59 I think the big problem is all the other I/O you lose, but it does remind me of a startup several years back that had a memory-encrypting hypervisor which itself booted and ran entirely out of cache so the actual RAM never had cleartext in it
       
 (DIR) Post #ATxQhsFk2LdLpmiisy by mjg59@nondeterministic.computer
       2023-03-25T00:38:48Z
       
       0 likes, 0 repeats
       
       @vivithecanine yes! One of the things that reminded me of it
       
 (DIR) Post #ATy46wZ92Dygf8k0R6 by gpshead@infosec.exchange
       2023-03-25T08:01:18Z
       
       0 likes, 0 repeats
       
       @mjg59 APUs have display hardware on die, does that _have_ to bypass the cache?... Regardless the bios starts entirely from cache and is responsible for configuring and initializing ram as one of its earlier tasks soo... just make your OS be Coreboot itself. And get creative with your own system design and abuse the memory controller configs to turn those hundreds of address and data lines into a huge pile of bitbanged HDMI ports! This is how you wind up on hackaday.
       
 (DIR) Post #ATymc9SNYKxbbSGezw by bwh@tech.lgbt
       2023-03-25T16:19:56Z
       
       0 likes, 0 repeats
       
       @mjg59 Intel has supported DDIO (DMA to/from cache) for a while, but I have no idea whether that works with cache-as-RAM
       
 (DIR) Post #ATyq7Ei0NLYujQ5gQq by gnomon@mastodon.social
       2023-03-25T16:59:12Z
       
       0 likes, 0 repeats
       
       @mjg59 dagnabbit, now you have me pondering whether the past tense should be "shitposted" or "shatpost"