Post Ax5aKW9BHLYStJIBfc by mntmn@mastodon.social
 (DIR) More posts by mntmn@mastodon.social
 (DIR) Post #Ax5VddyftDfCuNg9Y0 by mntmn@mastodon.social
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       this looks very interesting and could be a great match for MNT devices, esp. as i see an I/O header  https://www.crowdsupply.com/securinghw/epic-erebus
       
 (DIR) Post #Ax5YAncxEW0IIiSOUy by de@noc.social
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       @mntmn Cute. Not sure about the PCIe IP though. Seems they are tinkering with their own implementation. As far as I know there  is no working open source PCIe core available yet.
       
 (DIR) Post #Ax5aKW9BHLYStJIBfc by mntmn@mastodon.social
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       @de do you mean for ecp5 specifically?
       
 (DIR) Post #Ax5aklMDLliPasu4My by de@noc.social
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       @mntmn Yes, though I am also not aware of an open source core for any other FPGA architecture.There is some work happening: https://github.com/enjoy-digital/litepcie/issues/20 At the moment there is no progress because everybody is involved in other projects.