Comments for 2017-05-07:

James Stanley (WWW) 2021-01-10
 Having already implemented my silly CPU with an FPGA, I think if I were to start again (and, I
 probably will, at some point) then I would go almost completely the opposite direction from the
 memory-to-memory model. I would rather have registers with load/store instructions, and then have
 all the other instructions operate on a set of exposed registers. Benefits of this system include:
 - reduce the number of clock cycles per instruction, because you don't need to do as many
   round-trips to RAM
 - reduce the number of states required for the state machine
 - simplify pointers: instead of having to write confusing self-modifying code, you can just do a
   couple of load instructions, or 3, or however many you want, to match the number of levels of
   indirection
 Essentially, when it's implemented in an FPGA (or in actual hardware) the memory-to-memory model
 just turns into the registers/load/store model, because you need to get the values into "registers"
 at some point, even though the registers aren't exposed in the ISA. Except now every instruction
 has mandatory loads and stores associated. Giving control of the loads/stores over to the
 programmer simplifies the CPU implementation and gives the programmer more control, at the expense
 of making compilers more complicated.
 Another benefit of having lots of registers is that for some simple applications you can run your
 program entirely out of ROM, with no RAM included in the machine at all, because all of the
 internal state can go in the registers. Although this is obviously less relevant today than it was
 in the 70s because RAM is so cheap now.
 James

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