verilog.st - enscript - GNU Enscript
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       ---
       verilog.st (3935B)
       ---
            1 /**
            2  * Name: verilog
            3  * Description: Verilog hardware description language
            4  * Author: Edward Arthur <eda@ultranet.com>
            5  */
            6 
            7 state verilog extends HighlightEntry
            8 {
            9   /* Verilog takes C++ style comments */
           10 
           11   /* Comments. */
           12   /\/\*/ {
           13     comment_face (true);
           14     language_print ($0);
           15     call (c_comment);
           16     comment_face (false);
           17   }
           18   /\/\// {
           19     comment_face (true);
           20     language_print ($0);
           21     call (eat_one_line);
           22     comment_face (false);
           23   }
           24 
           25   /* String constants. */
           26   /\"/ {
           27     string_face (true);
           28     language_print ($0);
           29     call (c_string);
           30     string_face (false);
           31   }
           32 
           33   /* Macro expansions start with '`' and continue one word. */
           34   /`([a-zA-Z_0-9]+)/ {
           35     reference_face (true);
           36     language_print ($0);
           37     reference_face (false);
           38   }
           39 
           40   /* Keywords.
           41      (build-re '(always and assign begin buf bufif0 bufif1 case casex
           42      casez cmos deassign default defparam disable edge else end endcase
           43      endmodule endfunction endprimitive endspecify endtable endtask event
           44      for force forever fork function highz0 highz1 if initial inout input
           45      integer join large macromodule medium module nand negedge nmos nor
           46      not notif0 notif1 or output parameter pmos posedge primitive pull0
           47      pull1 pullup pulldown rcmos reg release repeat rnmos rpmos rtran
           48      rtranif0 rtranif1 scalared small specify specparam strength strong0
           49      strong1 supply0 supply1 table task time tran tranif0 tranif1 tri tri0
           50      tri1 triand trior trireg vectored wait wand weak0 weak1 while wire wor
           51      xnor xor
           52      $bitstoreal $countdrivers $display $fclose $fdisplay $fmonitor
           53      $fopen $fstrobe $fwrite $finish $getpattern $history $incsave $input
           54      $itor $key $list $log $monitor $monitoroff $monitoron $nokey $nolog
           55      $printtimescale $readmemb $readmemh $realtime $realtobits $reset
           56      $reset_count $reset_value $restart $rtoi $save $scale $scope
           57      $showscopes $showvariables $showvars $sreadmemb $sreadmemh $stime
           58      $stop $strobe $time $timeformat $write $vcdpluson $vcdplusoff
           59      $vcdplustraceon $vcdplustraceoff $dumpvars
           60      ;; prefix G stands for grave `
           61      Gaccelerate Gautoexpand_vectornets Gcelldefine Gdefault_nettype Gdefine
           62      Gelse Gendcelldefine Gendif Gendprotect Gendprotected
           63      Gexpand_vectornets Gifdef Ginclude Gnoaccelerate
           64      Gnoexpand_vectornets Gnoremove_gatenames Gnoremove_netnames
           65      Gnounconnected_drive Gprotect Gprotected Gremove_gatenames
           66      Gremove_netnames Gresetall Gtimescale Gunconnected_drive
           67      Guselib
           68      ))
           69    */
           70   /\$(bitstoreal|countdrivers|d(isplay|umpvars)\
           71 |f(close|display|inish|monitor|open|strobe|write)|getpattern|history\
           72 |i(n(csave|put)|tor)|key|l(ist|og)|monitor(|o(ff|n))|no(key|log)\
           73 |printtimescale\
           74 |r(e(a(dmem(b|h)|lt(ime|obits))|s(et(|_(count|value))|tart))|toi)\
           75 |s(ave|c(ale|ope)|how(scopes|var(iables|s))|readmem(b|h)|t(ime|op|robe))\
           76 |time(|format)|vcdplus(o(ff|n)|traceo(ff|n))|write)\b\
           77 |`(a(ccelerate|utoexpand_vectornets)|celldefine|def(ault_nettype|ine)\
           78 |e(lse|nd(celldefine|if|protect(|ed))|xpand_vectornets)|i(fdef|nclude)\
           79 |no(accelerate|expand_vectornets|remove_(gatenames|netnames)\
           80 |unconnected_drive)\
           81 |protect(|ed)|re(move_(gatenames|netnames)|setall)|timescale\
           82 |u(nconnected_drive|selib))\b\
           83 |\b(a(lways|nd|ssign)|b(egin|uf(|if(0|1)))|c(ase(|x|z)|mos)\
           84 |d(e(assign|f(ault|param))|isable)\
           85 |e(dge|lse|nd(|case|function|module|primitive|specify|ta(ble|sk))|vent)\
           86 |f(or(|ce|ever|k)|unction)|highz(0|1)|i(f|n(itial|out|put|teger))|join\
           87 |large|m(acromodule|edium|odule)|n(and|egedge|mos|o(r|t(|if(0|1))))\
           88 |o(r|utput)|p(arameter|mos|osedge|rimitive|ull(0|1|down|up))\
           89 |r(cmos|e(g|lease|peat)|nmos|pmos|tran(|if(0|1)))\
           90 |s(calared|mall|pec(ify|param)|tr(ength|ong(0|1))|upply(0|1))\
           91 |t(a(ble|sk)|ime|r(an(|if(0|1))|i(|0|1|and|or|reg)))|vectored\
           92 |w(a(it|nd)|eak(0|1)|hile|ire|or)|x(nor|or))\b/ {
           93     keyword_face (true);
           94     language_print ($0);
           95     keyword_face (false);
           96   }
           97 }
           98 
           99 
          100 /*
          101 Local variables:
          102 mode: c
          103 End:
          104 */