@DATABASE Hardware Manual
@NODE MAIN
@INDEX Hard_Index/MAIN
@TOC Hardware_Manual/MAIN
@TITLE "Amiga Hardware Reference Manual: List of Figures"
@{" Figure 1-1: Block Diagram for the Amiga Computer Family " link "ADCD_v1.2:reference_library/Hard_Pics/1-1.iff/Main"}
@{" Figure 2-1: Interlaced Bitplane in RAM " link ADCD_v1.2:Reference_Library/Hardware/Hard_2/2-8-4 12}
@{" Figure 3-1: How the Video Display Picture Is Produced " link ADCD_v1.2:Reference_Library/Hardware/Hard_3/3-1-1 7}
@{" Figure 3-2: What Is a Pixel? " link ADCD_v1.2:Reference_Library/Hardware/Hard_3/3-1-1 40}
@{" Figure 3-3: How Bitplanes Select a Color " link ADCD_v1.2:Reference_Library/Hardware/Hard_3/3-1-1 138}
@{" Figure 3-4: Significance of Bitplane Data in Selecting Colors " link ADCD_v1.2:Reference_Library/Hardware/Hard_3/3-1-1 182}
@{" Figure 3-5: Interlacing " link ADCD_v1.2:Reference_Library/Hardware/Hard_3/3-2-3 34}
@{" Figure 3-6: Effect of Interlaced Mode on Edges of Objects " link ADCD_v1.2:Reference_Library/Hardware/Hard_3/3-2-3 71}
@{" Figure 3-7: Memory Organization for a Basic Bitplane " link ADCD_v1.2:Reference_Library/Hardware/Hard_3/3-2-4-1 12}
@{" Figure 3-8: Combining Bitplanes " link ADCD_v1.2:Reference_Library/Hardware/Hard_3/3-2-5-2 9}
@{" Figure 3-9: Positioning the On-screen Display " link ADCD_v1.2:Reference_Library/Hardware/Hard_3/3-2-6 48}
@{" Figure 3-10: Data Fetched for the First Line When Modulo = 0 " link ADCD_v1.2:Reference_Library/Hardware/Hard_3/3-2-7 67}
@{" Figure 3-11: Data Fetched for the Second Line When Modulo = 0 " link ADCD_v1.2:Reference_Library/Hardware/Hard_3/3-2-7 91}
@{" Figure 3-12: A Dual-playfield Display " link "ADCD_v1.2:reference_library/Hard_Pics/3-12.iff/Main"}
@{" Figure 3-13: How Bitplanes Are Assigned to Dual Playfields " link ADCD_v1.2:Reference_Library/Hardware/Hard_3/3-3-1 12}
@{" Figure 3-14: Memory Picture Larger than the Display " link ADCD_v1.2:Reference_Library/Hardware/Hard_3/3-4-1-1 9}
@{" Figure 3-15: Data Fetch for the First Line When Modulo = 40 " link ADCD_v1.2:Reference_Library/Hardware/Hard_3/3-4-1-1 29}
@{" Figure 3-16: Data Fetch for the Second Line When Modulo = 40 " link ADCD_v1.2:Reference_Library/Hardware/Hard_3/3-4-1-1 53}
@{" Figure 3-17: Data Layout for First Line -- Right Half of Big Picture " link ADCD_v1.2:Reference_Library/Hardware/Hard_3/3-4-1-1 71}
@{" Figure 3-18: Data Layout for Second Line -- Right Half of Big Picture " link ADCD_v1.2:Reference_Library/Hardware/Hard_3/3-4-1-1 88}
@{" Figure 3-19: Display Window Horizontal Starting Position " link ADCD_v1.2:Reference_Library/Hardware/Hard_3/3-4-1-4 7}
@{" Figure 3-20: Display Window Vertical Starting Position " link ADCD_v1.2:Reference_Library/Hardware/Hard_3/3-4-1-4 31}
@{" Figure 3-21: Display Window Horizontal Stopping Position " link ADCD_v1.2:Reference_Library/Hardware/Hard_3/3-4-1-5 7}
@{" Figure 3-22: Display Window Vertical Stopping Position " link ADCD_v1.2:Reference_Library/Hardware/Hard_3/3-4-1-5 31}
@{" Figure 3-23: Vertical Scrolling " link "ADCD_v1.2:reference_library/Hard_Pics/3-23.iff/Main"}
@{" Figure 3-24: Horizontal Scrolling " link "ADCD_v1.2:reference_library/Hard_Pics/3-24.iff/Main"}
@{" Figure 3-25: Memory Picture Larger Than the Display Window " link ADCD_v1.2:Reference_Library/Hardware/Hard_3/3-5-2-2 6}
@{" Figure 3-26: Data for Line 1 - Horizontal Scrolling " link ADCD_v1.2:Reference_Library/Hardware/Hard_3/3-5-2-2 23}
@{" Figure 3-27: Data for Line 2 - Horizontal Scrolling " link ADCD_v1.2:Reference_Library/Hardware/Hard_3/3-5-2-2 39}
@{" Figure 4-1: Defining Sprite On-screen Position " link ADCD_v1.2:Reference_Library/Hardware/Hard_4/4-2-1 10}
@{" Figure 4-2: Position of Sprites " link ADCD_v1.2:Reference_Library/Hardware/Hard_4/4-2-1-1 38}
@{" Figure 4-3: Shape of Spaceship " link ADCD_v1.2:Reference_Library/Hardware/Hard_4/4-2-3 8}
@{" Figure 4-4: Sprite with Spaceship Shape Defined " link ADCD_v1.2:Reference_Library/Hardware/Hard_4/4-2-3 18}
@{" Figure 4-5: Sprite Color Definition " link ADCD_v1.2:Reference_Library/Hardware/Hard_4/4-2-4 5}
@{" Figure 4-6: Color Register Assignments " link ADCD_v1.2:Reference_Library/Hardware/Hard_4/4-2-4 42}
@{" Figure 4-7: Data Structure Layout " link ADCD_v1.2:Reference_Library/Hardware/Hard_4/4-2-6 57}
@{" Figure 4-8: Sprite Priority " link ADCD_v1.2:Reference_Library/Hardware/Hard_4/4-5-1 13}
@{" Figure 4-9: Typical Example of Sprite Reuse " link ADCD_v1.2:Reference_Library/Hardware/Hard_4/4-6 8}
@{" Figure 4-10: Typical Data Structure for Sprite Re-use " link ADCD_v1.2:Reference_Library/Hardware/Hard_4/4-6 43}
@{" Figure 4-11: Overlapping Sprites (Not Attached) " link "ADCD_v1.2:reference_library/Hard_Pics/4-11.iff/Main"}
@{" Figure 4-12: Placing Sprites Next to Each Other " link ADCD_v1.2:Reference_Library/Hardware/Hard_4/4-7 19}
@{" Figure 4-13: Sprite Control Circuitry " link "ADCD_v1.2:reference_library/Hard_Pics/4-13.iff/Main"}
@{" Figure 5-1: Sine Waveform " link "ADCD_v1.2:reference_library/Hard_Pics/5-1.iff/Main"}
@{" Figure 5-2: Digitized Amplitude Values " link "ADCD_v1.2:reference_library/Hard_Pics/5-2.iff/Main"}
@{" Figure 5-3: Example Sine Wave " link "ADCD_v1.2:reference_library/Hard_Pics/5-3.iff/Main"}
@{" Figure 5-4: Waveform with Multiple Cycles " link "ADCD_v1.2:reference_library/Hard_Pics/5-4.iff/Main"}
@{" Figure 5-5: Frequency Domain Plot of Low-Pass Filter " link ADCD_v1.2:Reference_Library/Hardware/Hard_5/5-4-5 12}
@{" Figure 5-6: Noise-free Output (No Aliasing Distortion) " link ADCD_v1.2:Reference_Library/Hardware/Hard_5/5-4-5 36}
@{" Figure 5-7: Some Aliasing Distortion " link ADCD_v1.2:Reference_Library/Hardware/Hard_5/5-4-5 61}
@{" Figure 5-8: Audio State Diagram " link "ADCD_v1.2:reference_library/Hard_Pics/5-8.iff/Main"}
@{" Figure 6-1: How Images are Stored in Memory " link ADCD_v1.2:Reference_Library/Hardware/Hard_6/6-3 41}
@{" Figure 6-2: BLTxPTR and BLTxMOD calculations " link ADCD_v1.2:Reference_Library/Hardware/Hard_6/6-3 143}
@{" Figure 6-3: Blitter Minterm Venn Diagram " link ADCD_v1.2:Reference_Library/Hardware/Hard_6/6-4-2 2}
@{" Figure 6-4: Extracting a Range of Columns " link ADCD_v1.2:Reference_Library/Hardware/Hard_6/6-5 75}
@{" Figure 6-5: Use of the FCI Bit - Bit Is a 0 " link ADCD_v1.2:Reference_Library/Hardware/Hard_6/6-8 39}
@{" Figure 6-6: Use of the FCI Bit - Bit Is a 1 " link ADCD_v1.2:Reference_Library/Hardware/Hard_6/6-8 62}
@{" Figure 6-7: Single-Point Vertex Example " link ADCD_v1.2:Reference_Library/Hardware/Hard_6/6-8 86}
@{" Figure 6-8: Octants for Line Drawing " link ADCD_v1.2:Reference_Library/Hardware/Hard_6/6-13 20}
@{" Figure 6-9: DMA Time Slot Allocation " link "ADCD_v1.2:reference_library/Hard_Pics/6-9.iff/Main"}
@{" Figure 6-10: Normal 68000 Cycle " link ADCD_v1.2:Reference_Library/Hardware/Hard_6/6-15 69}
@{" Figure 6-11: Time Slots Used by a Six Bitplane Display " link ADCD_v1.2:Reference_Library/Hardware/Hard_6/6-15 103}
@{" Figure 6-12: Time Slots Used by a High Resolution Display " link ADCD_v1.2:Reference_Library/Hardware/Hard_6/6-15 123}
@{" Figure 6-13: Blitter Block Diagram " link "ADCD_v1.2:reference_library/Hard_Pics/6-13.iff/Main"}
@{" Figure 7-1: Inter-Sprite Fixed Priorities " link ADCD_v1.2:Reference_Library/Hardware/Hard_7/7-1-1 5}
@{" Figure 7-2: Analogy for Video Priority " link "ADCD_v1.2:reference_library/Hard_Pics/7-2.iff/Main"}
@{" Figure 7-3: Sprite/Playfield Priority " link ADCD_v1.2:Reference_Library/Hardware/Hard_7/7-1-4 76}
@{" Figure 7-4: Interrupt Priorities " link ADCD_v1.2:Reference_Library/Hardware/Hard_7/7-4-5-10}
@{" Figure 8-1: Controller Plug and Computer Connector " link "ADCD_v1.2:reference_library/Hard_Pics/8-1.iff/Main"}
@{" Figure 8-2: Mouse Quadrature " link ADCD_v1.2:Reference_Library/Hardware/Hard_8/8-1-2 10}
@{" Figure 8-3: Joystick to Counter Connections " link "ADCD_v1.2:reference_library/Hard_Pics/8-3.iff/Main"}
@{" Figure 8-4: Typical Paddle Wiring Diagram " link ADCD_v1.2:Reference_Library/Hardware/Hard_8/8-1-4 9}
@{" Figure 8-5: Effects of Resistance on Charging Rate " link "ADCD_v1.2:reference_library/Hard_Pics/8-5.iff/Main"}
@{" Figure 8-6: Potentiometer Charging Circuit " link "ADCD_v1.2:reference_library/Hard_Pics/8-6.iff/Main"}
@{" Figure 8-7: Chinon Write Timing Diagram " link ADCD_v1.2:Reference_Library/Hardware/Hard_8/8-2-2 6}
@{" Figure 8-8: Chinon Access Timing Diagram " link ADCD_v1.2:Reference_Library/Hardware/Hard_8/8-2-2 42}
@{" Figure 8-9: Chinon Read Timing Diagram " link ADCD_v1.2:Reference_Library/Hardware/Hard_8/8-2-2 68}
@{" Figure 8-10: The Amiga 1000 Keyboard " link "ADCD_v1.2:reference_library/Hard_Pics/8-10.iff/Main"}
@{" Figure 8-11: The Amiga 500/2000/3000 Keyboard " link "ADCD_v1.2:reference_library/Hard_Pics/8-11.iff/Main"}
@{" Figure 8-12: Starting Appearance of SERDAT and Shift Register " link ADCD_v1.2:Reference_Library/Hardware/Hard_8/8-4-5 22}
@{" Figure 8-13: Ending Appearance of Shift Register " link ADCD_v1.2:Reference_Library/Hardware/Hard_8/8-4-5 38}
@{" Figure D-1: Amiga 3000 Memory Map " link ADCD_v1.2:Reference_Library/Hardware/Hard_D/D-2 55}
@{" Figure E-1: Reading Fire Buttons " link ADCD_v1.2:Reference_Library/Hardware/Hard_E/E-2-3-3 34}
@{" Figure E-2: Pot Counters " link ADCD_v1.2:Reference_Library/Hardware/Hard_E/E-2-3-4 59}
@{" Figure E-3: Light Pen " link ADCD_v1.2:Reference_Library/Hardware/Hard_E/E-2-3-5 28}
@{" Figure K-1: Expansion Memory Map " link ADCD_v1.2:Reference_Library/Hardware/Hard_K/K-1-3 35}
@{" Figure K-2: A2000 vs A3000 Bus Termination " link ADCD_v1.2:Reference_Library/Hardware/Hard_K/K-2-1-7 19}
@{" Figure K-3: Expansion Bus Clocks " link ADCD_v1.2:Reference_Library/Hardware/Hard_K/K-2-3-2 33}
@{" Figure K-4: Zorro II Bus Arbitration " link ADCD_v1.2:Reference_Library/Hardware/Hard_K/K-2-3-5 28}
@{" Figure k-5: Basic Zorro III Cycle " link ADCD_v1.2:Reference_Library/Hardware/Hard_K/K-3-1-2 7}
@{" Figure K-6: Multiple Transfer Cycles " link ADCD_v1.2:Reference_Library/Hardware/Hard_K/K-3-3 31}
@{" Figure K-7: Zorro III Bus Arbitration " link ADCD_v1.2:Reference_Library/Hardware/Hard_K/K-3-4 42}
@{" Figure K-8: Interrupt Vector Cycle " link ADCD_v1.2:Reference_Library/Hardware/Hard_K/K-3-5 16}
@{" Figure K-9: Zorro II Within Zorro III " link ADCD_v1.2:Reference_Library/Hardware/Hard_K/K-3-6 10}
@{" Figure K-10: Read Cycle Timing " link ADCD_v1.2:Reference_Library/Hardware/Hard_K/K-5-1 15}
@{" Figure K-11: Write Cycle Timing " link ADCD_v1.2:Reference_Library/Hardware/Hard_K/K-5-2 15}
@{" Figure K-12: Multiple Transfer Cycle Timing " link ADCD_v1.2:Reference_Library/Hardware/Hard_K/K-5-3 19}
@{" Figure K-13: Quick Interrupt Cycle Timing " link ADCD_v1.2:Reference_Library/Hardware/Hard_K/K-5-4 16}
@{" Figure K-14: Basic Zorro III Pic " link ADCD_v1.2:Reference_Library/Hardware/Hard_K/K-7-1 3}
@{" Figure K-15: Pic with ISA Option " link ADCD_v1.2:Reference_Library/Hardware/Hard_K/K-7-2 3}
@{" Figure K-16: Pic with Video Option " link ADCD_v1.2:Reference_Library/Hardware/Hard_K/K-7-3 6}
@{" Figure K-17: Configuration Register Map " link ADCD_v1.2:Reference_Library/Hardware/Hard_K/K-8-1 46}

@ENDNODE
