@DATABASE Hardware Manual
@NODE MAIN "Amiga Hardware Reference Manual: B Register Summary Address Order"
@INDEX Hard_Index/MAIN
@TOC Hardware_Manual/MAIN
This appendix contains information about the register set in address order.

The following codes and abbreviations are used in this appendix:

  &        Register used by DMA channel only.

  %        Register used by DMA channel usually, processors sometimes.

  +        Address register pair.  Must be an even address pointing to chip
           memory.

  *        Address not writable by the Copper.

  ~        Address not writable by the Copper unless the "copper danger
           bit", @{" COPCON " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-26} is set true.

  A,D,P    A=Agnus chip, D=Denise chip, P=Paula chip.

  W,R      W=write-only; R=read-only,

  ER       Early read. This is a DMA data transfer to RAM, from either the
           disk or the blitter.  RAM timing requires data to be on the bus
           earlier than microprocessor read cycles. These transfers are
           therefore initiated by Agnus timing, rather than a read address
           on the destination address bus.

  S        Strobe (write address with no register bits).  Writing the
           register causes the effect.

  PTL,PTH  Chip memory pointer that addresses DMA data.  Must be reloaded
           by a processor before use (vertical blank for bitplane and
           sprite pointers, and prior to starting the blitter for blitter
           pointers).

  LCL,LCH  Chip memory location (starting address) of DMA data.  Used to
           automatically restart pointers, such as the Copper program
           counter (during vertical blank) and the audio sample counter
           (whenever the audio length count is finished).

  MOD      15-bit modulo. A number that is automatically added to the
           memory address at the end of each line to generate the address
           for the beginning of the next line. This allows the blitter (or
           the display window) to operate on (or display) a window of data
           that is smaller than the actual picture in memory (memory map).
           Uses 15 bits, plus sign extend.

   About the ECS registers.
   ------------------------
   Registers denoted with an "(E)" in the chip column means that
   those registers have been changed in the Enhanced Chip Set
   (ECS).  The ECS is found in the A3000, and is installable in the
   A500 and A2000.  Certain ECS registers are completely new,
   others have been extended in their functionality. See the
   @{" register map " link ADCD_v1.2:Reference_Library/Hardware/Hard_C/C-3} in Appendix C for information on which ECS
   registers are new and which have been modified.

----------------------------------------------------------------------
NAME        ADD  R/W  CHIP    FUNCTION
----------------------------------------------------------------------
@{" BLTDDAT " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-11}  & *000  ER  A       Blitter destination early read
                                   (dummy address)
@{" DMACONR " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-32}    *002  R   AP      DMA control (and blitter status) read
@{" VPOSR " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-55}      *004  R   A(@{" E " link ADCD_v1.2:Reference_Library/Hardware/Hard_C/C-2-1})  Read vert most signif. bit (and frame flop)
@{" VHPOSR " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-54}     *006  R   A       Read vert and horiz. position of beam
@{" DSKDATR " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-34}  & *008  ER  P       Disk data early read (dummy address)
@{" JOY0DAT " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-41}    *00A  R   D       Joystick-mouse 0 data (vert,horiz)
@{" JOY1DAT " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-41}    *00C  R   D       Joystick-mouse 1 data (vert,horiz)
@{" CLXDAT " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-23}     *00E  R   D       Collision data register (read and clear)
@{" ADKCONR " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-1}    *010  R   P       Audio, disk control register read
@{" POT0DAT " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-43}    *012  R   P(@{" E " link ADCD_v1.2:Reference_Library/Hardware/Hard_C/C-2-11})  Pot counter pair 0 data (vert,horiz)
@{" POT1DAT " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-43}    *014  R   P(@{" E " link ADCD_v1.2:Reference_Library/Hardware/Hard_C/C-2-11})  Pot counter pair 1 data (vert,horiz)
@{" POTGOR " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-44}     *016  R   P       Pot port data read (formerly POTINP)
@{" SERDATR " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-46 22}    *018  R   P       Serial port data and status read
@{" DSKBYTR " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-33}    *01A  R   P       Disk data byte and status read
@{" INTENAR " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-39}    *01C  R   P       Interrupt enable bits read
@{" INTREQR " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-40}    *01E  R   P       Interrupt request bits read
@{" DSKPTH " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-36}   + *020  W   A(@{" E " link ADCD_v1.2:Reference_Library/Hardware/Hard_C/C-2-10 4})  Disk pointer (high 3 bits, 5 bits if ECS)
@{" DSKPTL " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-36}   + *022  W   A       Disk pointer (low 15 bits)
@{" DSKLEN " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-35}     *024  W   P       Disk length
@{" DSKDAT " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-34}   & *026  W   P       Disk DMA data write
@{" REFPTR " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-45}   & *028  W   A       Refresh pointer
@{" VPOSW " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-55}      *02A  W   A       Write vert most signif. bit (and frame flop)
@{" VHPOSW " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-54}     *02C  W   A       Write vert and horiz position of beam
@{" COPCON " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-26}     *02E  W   A(@{" E " link ADCD_v1.2:Reference_Library/Hardware/Hard_C/C-2-11 17})  Coprocessor control register (CDANG)
@{" SERDAT " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-46}     *030  W   P       Serial port data and stop bits write
@{" SERPER " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-47}     *032  W   P       Serial port period and control
@{" POTGO " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-44}      *034  W   P       Pot port data write and start
@{" JOYTEST " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-42}    *036  W   D       Write to all four joystick-mouse counters
                               at once
@{" STREQU " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-52}   & *038  S   D       Strobe for horiz sync with VB and EQU
@{" STRVBL " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-52 19}   & *03A  S   D       Strobe for horiz sync with VB (vert. blank)
@{" STRHOR " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-52}   & *03C  S   DP      Strobe for horiz sync
@{" STRLONG " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-52}  & *03E  S   D(@{" E " link ADCD_v1.2:Reference_Library/Hardware/Hard_C/C-2-10 18})  Strobe for identification of long
                                   horiz. line.
@{" BLTCON0 " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-9}    ~040  W   A       Blitter control register 0
@{" BLTCON1 " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-9}    ~042  W   A(@{" E " link ADCD_v1.2:Reference_Library/Hardware/Hard_C/C-2-10 26})  Blitter control register 1
@{" BLTAFWM " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-8}    ~044  W   A       Blitter first word mask for source A
@{" BLTALWM " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-8}    ~046  W   A       Blitter last word mask for source A
@{" BLTCPTH " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-16}  + ~048  W   A       Blitter pointer to source C (high 3 bits)
@{" BLTCPTL " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-16}  + ~04A  W   A       Blitter pointer to source C (low 15 bits)
@{" BLTBPTH " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-16}  + ~04C  W   A       Blitter pointer to source B (high 3 bits)
@{" BLTBPTL " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-16}  + ~04E  W   A       Blitter pointer to source B (low 15 bits)
@{" BLTAPTH " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-16}  + ~050  W   A(@{" E " link ADCD_v1.2:Reference_Library/Hardware/Hard_C/C-2-10 4})  Blitter pointer to source A (high 3 bits)
@{" BLTAPTL " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-16}  + ~052  W   A       Blitter pointer to source A (low 15 bits)
@{" BLTDPTH " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-16}  + ~054  W   A       Blitter pointer to destination D
                                   (high 3 bits)
@{" BLTDPTL " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-16}  + ~056  W   A       Blitter pointer to destination D
                                   (low 15 bits)
@{" BLTSIZE " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-12}    ~058  W   A       Blitter start and size (window width,height)
@{" BLTCON0L " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-10}   ~05A  W   A(@{" E " link ADCD_v1.2:Reference_Library/Hardware/Hard_C/C-2-10 34})  Blitter control 0, lower 8 bits (minterms)
@{" BLTSIZV " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-12 28}    ~05C  W   A(@{" E " link ADCD_v1.2:Reference_Library/Hardware/Hard_C/C-2-9 13})  Blitter V size (for 15 bit vertical size)
@{" BLTSIZH " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-12 28}    ~05E  W   A(@{" E " link ADCD_v1.2:Reference_Library/Hardware/Hard_C/C-2-9 13})  Blitter H size and start (for 11 bit H size)
@{" BLTCMOD " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-15}    ~060  W   A       Blitter modulo for source C
@{" BLTBMOD " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-15}    ~062  W   A       Blitter modulo for source B
@{" BLTAMOD " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-15}    ~064  W   A       Blitter modulo for source A
@{" BLTDMOD " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-15}    ~066  W   A       Blitter modulo for destination D
             ~068
             ~06A
             ~06C
             ~06E
@{" BLTCDAT " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-14}  % ~070  W   A       Blitter source C data register
@{" BLTBDAT " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-14}  % ~072  W   A       Blitter source B data register

@{" BLTADAT " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-14}  % ~074  W   A       Blitter source A data register
             ~076
 SPRHDAT     ~078  W   A( E )  Ext. logic UHRES sprite pointer and data id
             ~07A
@{" DENISEID " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-30}   ~07C  R   D(@{" E " link ADCD_v1.2:Reference_Library/Hardware/Hard_C/C-2-1 21})  Chip revision level for Denise
                                   (video out chip)
@{" DSKSYNC " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-37}    ~07E  W   P       Disk sync pattern register for disk read
@{" COP1LCH " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-25}  +  080  W   A(@{" E " link ADCD_v1.2:Reference_Library/Hardware/Hard_C/C-2-10 4})  Coprocessor first location register
                                  (high 3 bits, high 5 bits if ECS)
@{" COP1LCL " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-25}  +  082  W   A       Coprocessor first location register
                                  (low 15 bits)
@{" COP2LCH " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-25}  +  084  W   A(@{" E " link ADCD_v1.2:Reference_Library/Hardware/Hard_C/C-2-10 4})  Coprocessor second location register
                                  (high 3 bits, high 5 bits if ECS)
@{" COP2LCL " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-25}  +  086  W   A       Coprocessor second location register
                                  (low 15 bits)
@{" COPJMP1 " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-28}     088  S   A       Coprocessor restart at first location
@{" COPJMP2 " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-28}     08A  S   A       Coprocessor restart at second location
@{" COPINS " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-27}      08C  W   A       Coprocessor instruction fetch identify
@{" DIWSTRT " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-31}     08E  W   A       Display window start (upper left
                                  vert-horiz position)
@{" DIWSTOP " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-31}     090  W   A       Display window stop (lower right
                                  vert.-horiz. position)
@{" DDFSTRT " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-29}     092  W   A       Display bitplane data fetch start
                                  (horiz. position)
@{" DDFSTOP " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-29}     094  W   A       Display bitplane data fetch stop
                                  (horiz. position)
@{" DMACON " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-32}      096  W   ADP     DMA control write (clear or set)
@{" CLXCON " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-22}      098  W   D       Collision control
@{" INTENA " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-39}      09A  W   P       Interrupt enable bits (clear or
                                  set bits)
@{" INTREQ " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-40}      09C  W   P       Interrupt request bits (clear or
                                  set bits)
@{" ADKCON " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-1}      09E  W   P       Audio, disk, UART control
@{" AUD0LCH " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-3}  +  0A0  W   A(@{" E " link ADCD_v1.2:Reference_Library/Hardware/Hard_C/C-2-10 4})  Audio channel 0 location (high 3 bits,
                                   5 if ECS)
@{" AUD0LCL " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-3}  +  0A2  W   A       Audio channel 0 location (low 15 bits)
@{" AUD0LEN " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-4}     0A4  W   P       Audio channel 0 length
@{" AUD0PER " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-5}     0A6  W   P(@{" E " link ADCD_v1.2:Reference_Library/Hardware/Hard_C/C-2-11 30})  Audio channel 0 period
@{" AUD0VOL " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-6}     0A8  W   P       Audio channel 0 volume
@{" AUD0DAT " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-2}  &  0AA  W   P       Audio channel 0 data
              0AC
              0AE
@{" AUD1LCH " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-3}  +  0B0  W   A       Audio channel 1 location (high 3 bits)
@{" AUD1LCL " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-3}  +  0B2  W   A       Audio channel 1 location (low 15 bits)
@{" AUD1LEN " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-4}     0B4  W   P       Audio channel 1 length
@{" AUD1PER " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-5}     0B6  W   P       Audio channel 1 period
@{" AUD1VOL " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-6}     0B8  W   P       Audio channel 1 volume
@{" AUD1DAT " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-2}  &  0BA  W   P       Audio channel 1 data
              0BC
              0BE
@{" AUD2LCH " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-3}  +  0C0  W   A       Audio channel 2 location (high 3 bits)
@{" AUD2LCL " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-3}  +  0C2  W   A       Audio channel 2 location (low 15 bits)
@{" AUD2LEN " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-4}     0C4  W   P       Audio channel 2 length
@{" AUD2PER " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-5}     0C6  W   P       Audio channel 2 period
@{" AUD2VOL " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-6}     0C8  W   P       Audio channel 2 volume
@{" AUD2DAT " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-2}  &  0CA  W   P       Audio channel 2 data
              0CC
              0CE
@{" AUD3LCH " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-3}  +  0D0  W   A       Audio channel 3 location (high 3 bits)
@{" AUD3LCL " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-3}  +  0D2  W   A       Audio channel 3 location (low 15 bits)
@{" AUD3LEN " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-4}     0D4  W   P       Audio channel 3 length
@{" AUD3PER " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-5}     0D6  W   P       Audio channel 3 period
@{" AUD3VOL " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-6}     0D8  W   P       Audio channel 3 volume
@{" AUD3DAT " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-2}  &  0DA  W   P       Audio channel 3 data
              0DC
              0DE
@{" BPL1PTH " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-21}  +  0E0  W   A       Bitplane 1 pointer (high 3 bits)
@{" BPL1PTL " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-21}  +  0E2  W   A       Bitplane 1 pointer (low 15 bits)
@{" BPL2PTH " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-21}  +  0E4  W   A       Bitplane 2 pointer (high 3 bits)
@{" BPL2PTL " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-21}  +  0E6  W   A       Bitplane 2 pointer (low 15 bits)
@{" BPL3PTH " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-21}  +  0E8  W   A       Bitplane 3 pointer (high 3 bits)
@{" BPL3PTL " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-21}  +  0EA  W   A       Bitplane 3 pointer (low 15 bits)
@{" BPL4PTH " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-21}  +  0EC  W   A       Bitplane 4 pointer (high 3 bits)
@{" BPL4PTL " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-21}  +  0EE  W   A       Bitplane 4 pointer (low 15 bits)
@{" BPL5PTH " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-21}  +  0F0  W   A       Bitplane 5 pointer (high 3 bits)
@{" BPL5PTL " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-21}  +  0F2  W   A       Bitplane 5 pointer (low 15 bits)
@{" BPL6PTH " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-21}  +  0F4  W   A       Bitplane 6 pointer (high 3 bits)
@{" BPL6PTL " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-21}  +  0F6  W   A       Bitplane 6 pointer (low 15 bits)
              0F8
              0FA
              0FC
              0FE
@{" BPLCON0 " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-18}     100  W   AD(@{" E " link ADCD_v1.2:Reference_Library/Hardware/Hard_C/C-2-2}) Bitplane control register
                                   (misc. control bits)
@{" BPLCON1 " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-18}     102  W   D       Bitplane control reg.
                                   (scroll value PF1, PF2)
@{" BPLCON2 " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-18}     104  W   D(@{" E " link ADCD_v1.2:Reference_Library/Hardware/Hard_C/C-2-8})  Bitplane control reg. (priority control)
@{" BPLCON3 " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-18 57}     106  W   D(@{" E " link ADCD_v1.2:Reference_Library/Hardware/Hard_C/C-2-8})  Bitplane control (enhanced features)

@{" BPL1MOD " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-17}     108  W   A       Bitplane modulo (odd planes)
@{" BPL2MOD " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-17}     10A  W   A       Bitplane modulo (even planes)
              10C
              10E
@{" BPL1DAT " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-20}  &  110  W   D       Bitplane 1 data (parallel-to-serial convert)
@{" BPL2DAT " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-20}  &  112  W   D       Bitplane 2 data (parallel-to-serial convert)
@{" BPL3DAT " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-20}  &  114  W   D       Bitplane 3 data (parallel-to-serial convert)
@{" BPL4DAT " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-20}  &  116  W   D       Bitplane 4 data (parallel-to-serial convert)
@{" BPL5DAT " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-20}  &  118  W   D       Bitplane 5 data (parallel-to-serial convert)
@{" BPL6DAT " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-20}  &  11A  W   D       Bitplane 6 data (parallel-to-serial convert)
              11C
              11E
@{" SPR0PTH " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-50}  +  120  W   A       Sprite 0 pointer (high 3 bits)
@{" SPR0PTL " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-50}  +  122  W   A       Sprite 0 pointer (low 15 bits)
@{" SPR1PTH " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-50}  +  124  W   A       Sprite 1 pointer (high 3 bits)
@{" SPR1PTL " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-50}  +  126  W   A       Sprite 1 pointer (low 15 bits)
@{" SPR2PTH " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-50}  +  128  W   A       Sprite 2 pointer (high 3 bits)
@{" SPR2PTL " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-50}  +  12A  W   A       Sprite 2 pointer (low 15 bits)
@{" SPR3PTH " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-50}  +  12C  W   A       Sprite 3 pointer (high 3 bits)
@{" SPR3PTL " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-50}  +  12E  W   A       Sprite 3 pointer (low 15 bits)
@{" SPR4PTH " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-50}  +  130  W   A       Sprite 4 pointer (high 3 bits)
@{" SPR4PTL " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-50}  +  132  W   A       Sprite 4 pointer (low 15 bits)
@{" SPR5PTH " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-50}  +  134  W   A       Sprite 5 pointer (high 3 bits)
@{" SPR5PTL " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-50}  +  136  W   A       Sprite 5 pointer (low 15 bits)
@{" SPR6PTH " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-50}  +  138  W   A       Sprite 6 pointer (high 3 bits)
@{" SPR6PTL " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-50}  +  13A  W   A       Sprite 6 pointer (low 15 bits)
@{" SPR7PTH " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-50}  +  13C  W   A       Sprite 7 pointer (high 3 bits)
@{" SPR7PTL " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-50}  +  13E  W   A       Sprite 7 pointer (low 15 bits)
@{" SPR0POS " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-48}  %  140  W   AD      Sprite 0 vert-horiz start position
                                  data
@{" SPR0CTL " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-48}  %  142  W   AD(@{" E " link ADCD_v1.2:Reference_Library/Hardware/Hard_C/C-2-4}) Sprite 0 vert stop position and
                                  control data
@{" SPR0DATA " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-49} %  144  W   D       Sprite 0 image data register A
@{" SPR0DATB " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-49} %  146  W   D       Sprite 0 image data register B
@{" SPR1POS " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-48}  %  148  W   AD      Sprite 1 vert-horiz start position
                                  data
@{" SPR1CTL " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-48}  %  14A  W   AD      Sprite 1 vert stop position and
                                  control data
@{" SPR1DATA " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-49} %  14C  W   D       Sprite 1 image data register A
@{" SPR1DATB " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-49} %  14E  W   D       Sprite 1 image data register B
@{" SPR2POS " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-48}  %  150  W   AD      Sprite 2 vert-horiz start position
                                  data
@{" SPR2CTL " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-48}  %  152  W   AD      Sprite 2 vert stop position and
                                  control data
@{" SPR2DATA " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-49} %  154  W   D       Sprite 2 image data register A
@{" SPR2DATB " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-49} %  156  W   D       Sprite 2 image data register B
@{" SPR3POS " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-48}  %  158  W   AD      Sprite 3 vert-horiz start position
                                  data
@{" SPR3CTL " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-48}  %  15A  W   AD      Sprite 3 vert stop position and
                                  control data
@{" SPR3DATA " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-49} %  15C  W   D       Sprite 3 image data register A
@{" SPR3DATB " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-49} %  15E  W   D       Sprite 3 image data register B
@{" SPR4POS " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-48}  %  160  W   AD      Sprite 4 vert-horiz start position
                                  data
@{" SPR4CTL " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-48}  %  162  W   AD      Sprite 4 vert stop position and
                                  control data
@{" SPR4DATA " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-49} %  164  W   D       Sprite 4 image data register A
@{" SPR4DATB " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-49} %  166  W   D       Sprite 4 image data register B
@{" SPR5POS " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-48}  %  168  W   AD      Sprite 5 vert-horiz start position
                                  data
@{" SPR5CTL " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-48}  %  16A  W   AD      Sprite 5 vert stop position and
                                  control data
@{" SPR5DATA " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-49} %  16C  W   D       Sprite 5 image data register A
@{" SPR5DATB " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-49} %  16E  W   D       Sprite 5 image data register B
@{" SPR6POS " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-48}  %  170  W   AD      Sprite 6 vert-horiz start position
                                  data
@{" SPR6CTL " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-48}  %  172  W   AD      Sprite 6 vert stop position and
                                  control data
@{" SPR6DATA " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-49} %  174  W   D       Sprite 6 image data register A
@{" SPR6DATB " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-49} %  176  W   D       Sprite 6 image data register B
@{" SPR7POS " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-48}  %  178  W   AD      Sprite 7 vert-horiz start position
                                  data
@{" SPR7CTL " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-48}  %  17A  W   AD      Sprite 7 vert stop position and
                                  control data
@{" SPR7DATA " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-49} %  17C  W   D       Sprite 7 image data register A
@{" SPR7DATB " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-49} %  17E  W   D       Sprite 7 image data register B
@{" COLOR00 " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-24}     180  W   D       Color table 00
@{" COLOR01 " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-24}     182  W   D       Color table 01
@{" COLOR02 " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-24}     184  W   D       Color table 02
@{" COLOR03 " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-24}     186  W   D       Color table 03
@{" COLOR04 " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-24}     188  W   D       Color table 04
@{" COLOR05 " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-24}     18A  W   D       Color table 05
@{" COLOR06 " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-24}     18C  W   D       Color table 06
@{" COLOR07 " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-24}     18E  W   D       Color table 07
@{" COLOR08 " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-24}     190  W   D       Color table 08
@{" COLOR09 " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-24}     192  W   D       Color table 09
@{" COLOR10 " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-24}     194  W   D       Color table 10
@{" COLOR11 " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-24}     196  W   D       Color table 11
@{" COLOR12 " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-24}     198  W   D       Color table 12
@{" COLOR13 " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-24}     19A  W   D       Color table 13
@{" COLOR14 " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-24}     19C  W   D       Color table 14
@{" COLOR15 " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-24}     19E  W   D       Color table 15
@{" COLOR16 " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-24}     1A0  W   D       Color table 16
@{" COLOR17 " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-24}     1A2  W   D       Color table 17
@{" COLOR18 " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-24}     1A4  W   D       Color table 18
@{" COLOR19 " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-24}     1A6  W   D       Color table 19
@{" COLOR20 " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-24}     1A8  W   D       Color table 20
@{" COLOR21 " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-24}     1AA  W   D       Color table 21
@{" COLOR22 " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-24}     1AC  W   D       Color table 22
@{" COLOR23 " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-24}     1AE  W   D       Color table 23
@{" COLOR24 " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-24}     1B0  W   D       Color table 24
@{" COLOR25 " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-24}     1B2  W   D       Color table 25
@{" COLOR26 " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-24}     1B4  W   D       Color table 26
@{" COLOR27 " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-24}     1B6  W   D       Color table 27
@{" COLOR28 " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-24}     1B8  W   D       Color table 28
@{" COLOR29 " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-24}     1BA  W   D       Color table 29
@{" COLOR30 " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-24}     1BC  W   D       Color table 30
@{" COLOR31 " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-24}     1BE  W   D       Color table 31

@{" HTOTAL " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-38}      1C0  W   A(@{" E " link ADCD_v1.2:Reference_Library/Hardware/Hard_C/C-2-5 8})  Highest number count, horiz line
                                   (VARBEAMEN=1)
@{" HSSTOP " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-38}      1C2  W   A(@{" E " link ADCD_v1.2:Reference_Library/Hardware/Hard_C/C-2-5 29})  Horizontal line position for HSYNC stop
@{" HBSTRT " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-38}      1C4  W   A(@{" E " link ADCD_v1.2:Reference_Library/Hardware/Hard_C/C-2-5 42})  Horizontal line position for HBLANK start
@{" HBSTOP " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-38}      1C6  W   A(@{" E " link ADCD_v1.2:Reference_Library/Hardware/Hard_C/C-2-5 42})  Horizontal line position for HBLANK stop
@{" VTOTAL " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-56}      1C8  W   A(@{" E " link ADCD_v1.2:Reference_Library/Hardware/Hard_C/C-2-5 21})  Highest numbered vertical line
                                   (VARBEAMEN=1)
@{" VSSTOP " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-56}      1CA  W   A(@{" E " link ADCD_v1.2:Reference_Library/Hardware/Hard_C/C-2-5 29})  Vertical line position for VSYNC stop
@{" VBSTRT " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-53}      1CC  W   A(@{" E " link ADCD_v1.2:Reference_Library/Hardware/Hard_C/C-2-5 42})  Vertical line for VBLANK start
@{" VBSTOP " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-53}      1CE  W   A(@{" E " link ADCD_v1.2:Reference_Library/Hardware/Hard_C/C-2-5 42})  Vertical line for VBLANK stop

              1D0              Reserved
              1D2              Reserved
              1D4              Reserved
              1D6              Reserved
              1D8              Reserved
              1DA              Reserved

@{" BEAMCON0 " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-7}    1DC  W   A(@{" E " link ADCD_v1.2:Reference_Library/Hardware/Hard_C/C-2-6})  Beam counter control register (SHRES,PAL)
@{" HSSTRT " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-38}      1DE  W   A(@{" E " link ADCD_v1.2:Reference_Library/Hardware/Hard_C/C-2-5 29})  Horizontal sync start (VARHSY)
@{" VSSTRT " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-56}      1E0  W   A(@{" E " link ADCD_v1.2:Reference_Library/Hardware/Hard_C/C-2-5 29})  Vertical sync start   (VARVSY)
@{" HCENTER " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-38}     1E2  W   A(@{" E " link ADCD_v1.2:Reference_Library/Hardware/Hard_C/C-2-5 29})  Horizontal position for Vsync on interlace
@{" DIWHIGH " link ADCD_v1.2:Reference_Library/Hardware/Hard_A/A-31}     1E4  W   AD(@{" E " link ADCD_v1.2:Reference_Library/Hardware/Hard_C/C-2-7 16}) Display window -  upper bits for start, stop


 RESERVED     1110X
 RESERVED     1111X
 NO-OP(NULL)  1FE

@ENDNODE
