MCLK - This is the DAC master clock, depending on the DAC you choose
the requirements may be different.  Systems using I2S to transfer
digital audio data don't usually require it (e.g.  to convert to
SPDIF).  It's typically an oversampled clock at 256 x Fs (ie.
11.289.600Hz for 44.1KHz).  It's typically the clock source for all
other clocks in the system.  According to the datasheet, this is an
input in the Pi implementation, and can be used to generate the other
clocks when the Pi is a clock master.  It shouldn't be required if the
Pi is a slave.

LRCLK - This serves two purposes.  It synchronizes the samples (ie.
times them vs.  the bit clock), signals which channel is being sent
(usually LEFT when low), and clocks the new samples into the DAC.  It
will have a frequency equal to Fs.

SCLK - This is the bit clock, an edge marks a bit in the incoming
serial stream.  This clock depends on the sample bit depth; for I2S
which is usually either 16b or 32b (padded if necessary).  It will be
at Fs * 2 * bits.

DIN - Data, MSB first.
