1cb
Subj : Re: Lock Free -- where to start
To   : comp.programming.threads
From : Oliver S.
Date : Tue Oct 04 2005 01:20 am

> A hazard pointer implementation with 2 memory barriers, one
> for release semantics and the other for the "store/load" barrier,
> on a 866 Mhz P3 with XCHG to simulate the membars is 81 nsec w/
> membars and 8 nsec w/o membars on a 1.2 Ghz powerpc it's

Eh, you don't need membars on x86 except for some SSE-operations.

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