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Subj : Re: Using hierarchical memory as an acquire memory barrier for dependent  loads
To   : comp.programming.threads,comp.arch
From : nmm1
Date : Mon Sep 12 2005 09:46 am


In article <wQ2Ve.21920$k22.1912@fe2.news.blueyonder.co.uk>,
David Hopwood <david.nospam.hopwood@blueyonder.co.uk> writes:
|> 
|> Cache is supposed to be a transparent abstraction. So is the TLB (software
|> TLBs notwithstanding). Breaking that will break anyone's ability to understand
|> what the system is doing, just in order to try (without necessarily succeeding)
|> to optimize something that isn't a performance bottleneck.

Don't be so certain of the last.  I see both cache and TLB handling
being a performance bottleneck on a daily basis, and one of the
solutions to this would involve making them more visible.


Regards,
Nick Maclaren.

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