51d
Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Alexander Terekhov
Date : Thu Sep 01 2005 12:46 pm


Joe Seigh wrote:
[...]
> > I just notice this in the Itanium System Architecture manual.
> >
> > 2.1.2 Loads and Stores
> > In the Itanium architecture, a load instruction has either unordered or
> > acquire semantics while a
> > store instruction has either unordered or release semantics. By using
> > acquire loads (ld.acq) and
> > release stores (st.rel), the memory reference stream of an Itanium-based
> > program can be made to
> > operate according to the IA-32 ordering model. The Itanium architecture
> > uses this behavior to
> > provide IA-32 compatibility. That is, an Itanium acquire load is
> > equivalent to an IA-32 load and an
> > Itanium release store is equivalent to an IA-32 store, from a memory
> > ordering perspective.
> >
> 
> Somebody 

You mean Seongbae, I suppose.

http://groups.google.com/group/comp.arch/msg/3caf416c5034ec96

>          on comp.arch has convinced me this is not so, that Itanium is
> emulating a stronger memory model to be on the safe side.  

Somebody (Seongbae) a bit later:

http://groups.google.com/group/comp.arch/msg/3a54d5343a336b76

regards,
alexander.

.

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