4b4
Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : David Hopwood
Date : Tue Aug 30 2005 09:06 pm

Chris Thomasson wrote:
> "Alexander Terekhov" <terekhov@web.de> wrote:
>>Joe Seigh wrote:
>>[...]
>>
>>>just trying to save Intel from themselves.  It's not a
>>>correctness of implementation issue, it's a performance
>>
>>Under x86 memory model, all loads (including dependent ones) behave
>>in-order with respect to preceding loads. Processor can perform out-
>>of-order speculative loads but they never yield incorrect results
>>(processor detects memory ordering violations and rolls back).
> 
> http://groups.google.com/group/comp.programming.threads/msg/68ba70e66d6b6ee9?hl=en
> 
> any thoughts? 

| acquire & release semantics ( st.rel / ld.acq ) are held for loads and
| stores to the same locations; [...]

Alexander claims that these semantics hold even for loads and stores to
different locations. See the example in

<http://groups.google.co.uk/group/comp.programming.threads/browse_thread/thread/920001c96b3ebe49/55c38ab444fcc426#55c38ab444fcc426>

-- 
David Hopwood <david.nospam.hopwood@blueyonder.co.uk>

.

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