77d
Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Joe Seigh
Date : Tue Aug 30 2005 08:06 am

Alexander Terekhov wrote:
> SSE2 extensions introduce two new fence instructions (LFENCE and 
> MFENCE) as companions to the SFENCE instruction introduced with SSE 
> extensions.
> 
> The LFENCE instruction establishes a memory fence for loads. It 
> guarantees ordering between two loads and prevents speculative loads 
> from passing the load fence (that is, no speculative loads are allowed 
> until all loads specified before the load fence have been 
> carried out).
> 
> The MFENCE instruction combines the functions of LFENCE and SFENCE by 
> establishing a memory fence for both loads and stores. It guarantees 
> that all loads and stores specified before the fence are globally 
> observable prior to any loads or stores being carried out after the 
> fence.
> ----
> 
> So part from the store-load fencing provided by mfence, SSE fence
> instructions has really nothing to do with "ordinary" memory under
> processor consistency memory model (load:acquire, store:release,
> and locked-stuff:release+acquire).
> 

The LFENCE and MFENCE  are introduced with SSE2 but where do you get
the idea that they are meant only for the SSE stuff?  There are
numerous places in the documentation that state the SSE instructions
and string instructions weaken the memory model for stores, hence
you see SFENCE mentioned as a way to fix that.  But I don't see any
places that mention the SSE instructions and string instructions weaken
the memory model for loads with corresponding recommendations of using
LFENCE or MFENCE to fix that.  All mention of LFENCE (apart from it
being part of SSE2 feature set) are SSE context free.


-- 
Joe Seigh

When you get lemons, you make lemonade.
When you get hardware, you make software.

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