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Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Joe Seigh
Date : Mon Aug 29 2005 06:13 pm

David Hopwood wrote:
> Joe Seigh wrote:
> 
>> David Hopwood wrote:
>>>
>>> *Oh*. Now I understand why their documentation doesn't make sense.
>>> They're taking an aspect of the implementation and calling it a memory
>>> model.
>>
>>
>> If I understand it correctly, the speculative loads aren't observable by
>> programs using normal memory.  You'd need a scope on the system bus to
>> notice them.  If loads are indeed in order then they shouldn't have
>> mentioned the phrase speculative or out-of-order w.r.t. loads.
> 
> 
> I have no objection to them describing both a model and an implementation.
> I do object to having to disentangle model and implementation issues all
> mashed together in the same section as if it weren't important to
> distinguish them.
> 
> Dijkstra was right (see the bits about Mary Shaw's presentation):
> <http://www.cs.utexas.edu/users/EWD/transcriptions/EWD06xx/EWD611.html>
> 
> The AMD docs are not much better in this respect.
> 

Unfortunately, they seem to be conflating semantics and implementation
in the C++ thread support stuff so the damage is propagating.

-- 
Joe Seigh

When you get lemons, you make lemonade.
When you get hardware, you make software.

.

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