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Subj : Re: CMPXCHG timing
To   : comp.programming.threads
From : Chris Thomasson
Date : Mon Apr 04 2005 11:44 pm

> :)) On all x86 'store' operation implemented with 'mov' instruction has
> 'release' semantic, i.e. every such store 'happens' only after every
> preceding memory access finished

It must be understood to everybody reading this that ia32 can, and will, 
reorder a store followed by a load from "another" location:

http://groups-beta.google.com/group/comp.programming.threads/msg/2f2ec4c60b6a5d7c
http://groups-beta.google.com/group/comp.std.c++/msg/e03d27981e6f8151

Explicit barriers are required in this case. You need them in Dekkers and/or 
Petersons algorithm for instance...

.

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