652
Subj : Re: CMPXCHG timing
To   : comp.programming.threads
From : David Schwartz
Date : Fri Apr 01 2005 02:30 pm


"Michael Pryhodko" <mpryhodko@westpac.com.au> wrote in message 
news:1112335465.229320.187400@l41g2000cwc.googlegroups.com...

> So far it looks like speaking to myself. :) Well, it seems I found why
> proposed code does not work. It seems that internal implementation of
> CMPXCHG does not conform microcode listed in Intel Architecture manual,
> i.e.:
> processor reads value from memory, compares it with EAX and if they are
> different processor WRITES BACK original value!! Shit!! Who and why
> decided to do that??? Until someone explains me reasons behind this
> decision I will consider it as very "bright" and "brilliant" move from
> Intel.

    This is well-documented behavior of the CMPXCHG function. The write is 
unconditional. You should not be complaining about this because if you want 
atomic behavior, you have to use the LOCK prefix anyway, in which case the 
write is harmless. If you don't want atomic behavior, implement the function 
yourself without the extra write.

    By the way, looking at all of your posts on this issue, I think you're 
totally barking up the wrong tree. Single instructions without the LOCK 
prefix are not atomic with respect to other processors anyway -- if they 
were, what would the LOCK prefix be for? And you cannot rely on instruction 
timings for synchronization because of things like cache misses, speculative 
reads, and so on.

    I suggest you think carefully about what you're trying to do.

    DS

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