Path: blue.weeg.uiowa.edu!news.uiowa.edu!uunet!news.claremont.edu!nntp-server.caltech.edu!nathan
From: nathan@cco.caltech.edu (Nathan Mates)
Newsgroups: comp.sys.apple2
Subject: Re: 6502/65c02 undocumented opcode tables ...
Date: 8 Aug 1994 04:27:40 GMT
Organization: California Institute of Technology, Pasadena
Lines: 68
Message-ID: <324c7s$k6p@gap.cco.caltech.edu>
References: <3243kb$2t2@harbinger.cc.monash.edu.au>
NNTP-Posting-Host: accord.cco.caltech.edu

In article <3243kb$2t2@harbinger.cc.monash.edu.au>,
Malcolm Herbert <mjher4@mdw058.cc.monash.edu.au> wrote:
>I have heard that there is a table somewhere, listing all the 6502 (and
>possibly the 65c02) undocumented opcodes ... all I know is that one of
>them had been given the mnemonic of HCF -- Halt and Catch Fire, since
>that's apparently the sort of thing it does to the CPU, throws it
>completely out of whack ...

   According to _Programming the 65816..._ by Lichty & Eyes, the
behavior of undocumented opcodes was random, and could vary from chip
to chip (and most likely, from manufacturer to manufacturer). In any
case, unless you are working on an emulator, using such opcodes is
definitely NOT recommended. The book also points out that the behavior
of these opcodes was stabilized for the 65C02, but they act like
no-operation codes. There are 2 variants of the 65C02, the standard
Western Design Center/Everybody else and the Rockwell variant.

   Since WDC expanded their 65C02 into the 65802/65816, the extra
opcodes in the Rockwell one (mostly ones useful for microcontrollers)
are a moot point. But, since you asked, here they are:

   All of these opcodes have 8 parts, depending on what bit they're
dependednt on. As usual, bit 7 is the high bit, bit 0 the lowest.

BBR: BBR0...BBR7. Branch on Bir Reset.
 Syntax: BBRx dp,Nearlabel
 Explanation: The specified bit in the zero page location specified in
the operand is tested. If it is clear (reset, 0) a branch is taken,
else, not. The branch is of the same form as other branches.
 Opcode: BBR0=0F, BBR1=1F... BBR7=7F
 Specs: 3 bytes/instruction, 5 cycles (seems to be constant)

BBS: BBS0...BBS7. Branch on Bit Set
 Just like BBR, but branches if the spseciifed bit on the zero page
location is set.
 Opcode: BBS0=8F, BBS1=9F... BBS7=FF

RMB: RMB0...RMB7. Reset Memory Bit
 Syntax: RMBx dp
 Explanaion: Clear the specified bit in the zero page memory location
specified in the operand.
 Opcode: RMB0=07, RMB1=17... RMB7=77.
 Specs: 2 bytes per instruction, 5 cycles. Affects no processor flags.

SMB: SMB0...SMB7. Set memory bit
 Just like RMB, but sets a bit in the specified ZP location.
 Opcode: SMB0=87, SMB1=97... SMB7=F7



   If you thinking of things where undefined opcodes did things like
"decremet a, and if the result is 5, execute a hard reset", that's the
domain of the 6510, used in the Commie 64 machines. Sorry, I don't
have any specs; ask around. For your info, on the 65816 (superset of
the 65C02), there are some interesting instructionss similar to
whatyou mentioned above. STP, Stop the Processor, DB, which
effictively kills the processor untila reset occurs. WAI, Wait for
Interrupt, CB, setsthe processor up to execute an interrupt, then
puts the processor to sleep until such a thing is recieved.


Nathan Mates

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