Path: ns-mx!hobbes.physics.uiowa.edu!news.iastate.edu!iscsvax.uni.edu!fisher2557 From: fisher2557@iscsvax.uni.edu Newsgroups: comp.sys.apple2 Subject: 65c02 video timing answered Message-ID: <1992Feb26.003751.2485@iscsvax.uni.edu> Date: 26 Feb 92 06:37:51 GMT References: <1992Feb24.225356.16536@cs.aukuni.ac.nz> Organization: University of Northern Iowa Lines: 46 In article <1992Feb24.225356.16536@cs.aukuni.ac.nz>, robert-s@cs.aukuni.ac.nz (Robert Sheehan ) writes: > In doc@pro-calgary.cts.com (Sean Dockery) writes: > >>I am currently in need of a wait routine that is CPU speed indepent. That >>is, I would like a wait routine that would be dependent upon the video >>blanking signal (which is 1/60 s for every machine that I know of). > > Just to put the spanner in the works. Apple //c's in Australia, New Zealand, > Ireland, England, and maybe other parts of Europe have 50 Hz screen refreshes. > I presume European IIe's are similar. I know this because I have timed VBL > interrupts on my //c. The //c does have interrupts and doesn't handle VBL the > same way as the IIe. > -- > ------- Robert Sheehan ---- robert-s@cs.aukuni.ac.nz ------------------------- It would be intricate, but possible. I have written special routines that utilize the hi-res screen refresh to calculate the exact number of clock cycles required to execute an instruction. If you would like to try it, do this: (1) clear the hi-res screen (2) poke in a $d5 at $2000 (3) poke in a $aa at $2004 (4) write a ml routine that loops doing a LDX $c054 immediately followed by a LDY $c054, and make sure the loop's cycle time does not evenly divide into 17,030 cycles (relatively prime, please) which is the exact number of cycles required to refresh and return. If it cannot find the pattern in k^2 loops, where k = the number of times the look can execute in one refresh, then it's not running at 1 mhz. (5) try poking in various values at $2001, 2002, and 2003 and if LDX gets a $d5 then store the LDY and check it to see what it gets at that mhz. I don't have anything but 1 mhz so you'll have to find out which locations flag which speeds. It's complicated, but I hope it helps. The value at $c054 (and lots of the other video switches) are equal to the byte being displayed. The image is refreshed from top to bottom, each line left to right. At 1 mhz, each byte requires 1 cycle to display, and a "linefeed" from right back to left and down a line requires 25 cycles --> total for each line = 40+25=65 cycles. 65*192 = 12,480 cycles to refresh all the screen, but a "form feed" back to the top requires an additional 4,550 cycles. (equal to 70 lines) 12,480+4,550 = 17,030 cycles. This is linked with the cpu clock, so it is 100% accurate with the cpu's cycle time. When counting cycles, beware of the branch across page boundaries! Your task is difficult, so I wish you luck. If I can be of further help, lemme know. FISHER2557@ISCSVAX.UNI.EDU Nathan Fisher