Posts by brouhaha@mastodon.social
 (DIR) Post #B81f2RsWIpTLR6nAdk by brouhaha@mastodon.social
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       I'm hoping to get over 200 MHz execution (so possibly over 100M instructions per second) from an AMD/Xilinx Artix-7 FPGA, but that may be overly optimistic.For comparison, Z80 instructions take a minimum of four clocks, and up to 23, while my core should still execute that Z80 23-clock instruction in one clock cycle (two if memory read/modify/write). Average clocks per instruction should well under three, maybe even under two.5/
       
 (DIR) Post #B81f2SyaDlusqCdWjI by brouhaha@mastodon.social
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       The performance improvements come from:* 32-bit memory for prefetch (only 8 and 16 but accesses for operands)* single-cycle instruction decode (even for four-byte instructions)* PC and 16-bit incrementer/adder in instruction decoder, not register file* 16-bit adder for effective address computation* 16 bits wide ALU in data path* 16-bit wide register file* BC, DE, HL, SP, IX, IY registers each have their own incrementer/decrementer by 1/2* RISC-like execution pipeline6/
       
 (DIR) Post #B81f2TrWvTrvacLPNI by brouhaha@mastodon.social
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       Zilog did parts of this in the Z380 and eZ80, which do have lower instruction cycle counts than the earlier Z80/Z180/Z280/Z800. By using the techniques I mentioned, I expect to do significantly better even than the Z380 and eZ80, though I am only initially implementing the Z80 and Z180 instructions.7/
       
 (DIR) Post #B81f2Uvox0tYuDMLhY by brouhaha@mastodon.social
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       Writing to addresses that are contained in the prefetch queue or execution pipeline will also cause a queue and pipeline flush, because self-modifying code is unfortunately not uncommon in 8080 and Z80 code.8/
       
 (DIR) Post #B81f2VmHnwrXWvuFTk by brouhaha@mastodon.social
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       The core also has separate instruction and data busses, so it can be run as a Harvard architecture machine. In an FPGA, dual-port block RAM can support simultaneous instruction fetch and operand read/write from the same cache or memory block. For memory outside that, a bus multiplexer will be provided, prioritizing the operand data accesses over instruction fetches.9/
       
 (DIR) Post #B81f2WvXX1rJ5vF9Xc by brouhaha@mastodon.social
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       After I get everything else working, I may consider trying to make LDIR and LDDR move four bytes per pair of bus cycles rather than one. Obviously that would involve widening the operand read/write data bus to 32-bits, which should be no big deal since the instruction data bus is already 32 bits.This would depend on the bus and memory supporting djngle-cycle unaligned access, which is already an optional bus feature.10/
       
 (DIR) Post #B81f2YzrpuVbVvHdZ2 by brouhaha@mastodon.social
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       CPIR/CPDR could possibly be sped up that way as well.11/
       
 (DIR) Post #B81hiNAGQ11Mt5D5zU by brouhaha@mastodon.social
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       @astraleureka I may try to make some money selling specific system upgrade boards first, but I do intend to release it under an open license after I fall to make any money on it.
       
 (DIR) Post #B81hiNekafPKPdTRVg by brouhaha@mastodon.social
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       @astraleureka In the unlikely event that I do make money on it, I'll still plan for an open release.
       
 (DIR) Post #B81hiOiKeprnh29ojQ by brouhaha@mastodon.social
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       @astraleureka As usual, the prospect of making any money is an "it would be nice" objective, but nowhere near the top objectives, which are:* increase my hardware design skills* have fun
       
 (DIR) Post #B821wnjqPdQqRU0hBg by brouhaha@mastodon.social
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       @astraleureka I don't expect it to seriously appeal to anyone other than retrocomputing hobbyists.If I'm reasonably successful with the FPGA, it would be really fun to tape out an ASIC, using a shuttle run.For either FPGA or ASIC, I consider it highly important to have AT LEAST 64K of on-chip RAM, and ideally 512K or 1M, supporting some of the existing bank-switching schemes.For a bank-switched system, changes to the map have to force a prefetch and pipeline flush (possibly conditional).
       
 (DIR) Post #B82b2Ri2j3GiFmavo0 by brouhaha@mastodon.social
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       @CursedSilicon @argv_minus_one @fivetonsflax @futurebird It was asymmetric because they want to partition the frequency spectrum used into separate upward and downward bands, to avoid the computationally heavy need for full echo cancellation, and they both expected and wanted end users to be mostly consumers of content, not producers.There was no _techincal_ reason it couldn't be reverse in the other direction, or fully symmetric (which existed: SDSL).1/
       
 (DIR) Post #B82b2SH8cZLE0d0xVY by brouhaha@mastodon.social
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       @CursedSilicon @argv_minus_one @fivetonsflax @futurebird Making the frequency/direction control dynamically adjust was entirely possible, but would have made the DSLAM and modems a little more expensive, so they chose not to.2/
       
 (DIR) Post #B89CYZVy6UZYypt93g by brouhaha@mastodon.social
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       @fribbledom Given how much money I just paid for 64 GiB of DDR5 ECC RDIMMs, I'm going to start billing all web sites that run JavaScript on my computer.
       
 (DIR) Post #B8sEFwCW88PKw4sTiK by brouhaha@mastodon.social
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       @ariadne Everyone hates their HOA, except the few bullies who manage to be in charge of them and make everyone else's life hell.
       
 (DIR) Post #B8sEUnDPovMtPZNhTs by brouhaha@mastodon.social
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       @ariadne It's a thankless job, which is why the worst sociopaths end up running them.
       
 (DIR) Post #B8sNoAYOAl60spVPXc by brouhaha@mastodon.social
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       @ariadne Techbros only have the most superficial takes on everything. No actual thought process involved.
       
 (DIR) Post #B9GOTQZbC6gnfLPPKS by brouhaha@mastodon.social
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       @gardiner_bryant That's a great offer!Too bad I can't take advantage of it, as I'm not a The Atlantic subscriber.:-)
       
 (DIR) Post #B9y6WrPy2cd4HX4Dtg by brouhaha@mastodon.social
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       @gutenberg_org 🎶 There's no need for me to be a wallflowerBecause now I'm living on blues power
       
 (DIR) Post #BAEr2aQ6lcyOfii7hw by brouhaha@mastodon.social
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       @ariadne I spend so little time looking at login screens that I don't really care what they look like, as long as they don't impede my logging in.