Newsgroups: comp.arch
Path: utzoo!utgpu!watserv1!watdragon!rose.waterloo.edu!ccplumb
From: ccplumb@rose.waterloo.edu (Colin Plumb)
Subject: Re: skip instructions
Message-ID: <1991May6.060341.4373@watdragon.waterloo.edu>
Keywords: VLSI, ARCON, RISC, intsructions, SKIP, pipeline
Sender: news@watdragon.waterloo.edu (News Owner)
Organization: University of Waterloo
References: <3446@charon.cwi.nl> <1991May5.162722.29507@berlioz.nsc.com> <1991May05.180933.23091@kithrup.COM>
Date: Mon, 6 May 1991 06:03:41 GMT
Lines: 94

sef@kithrup.COM (Sean Eric Fagan) wrote:
> There are four bits in every instruction (the first four, in fact).  If I
> could find my ARM manual, I could even tell you what they were 8-(.

The high 4 bits in each instruction are a condition.  If the condition is
false, even illegal encodings are ignored.

For the trivia-minded,

0000 - EQ - Z=1
0001 - NE - Z=0
0010 - CS - C=1
0011 - CC - C=0
0100 - MI - N=1
0101 - PL - N=0
0110 - VS - V=1
0111 - VC - V=0
1000 - HI - C=1 & Z=0
1001 - LS - C=0 | Z=1
1010 - GE - N=V
1011 - LT - N!=V
1100 - GT - Z=0 & N=V
1101 - LE - Z=1 | N!=V
1110 - AL - Always
1111 - NV - Never

There are 16 registers, R15 is the PC and condition code register.  The low
2 bits are mode (00 = user) and the upper 6 are NZCVIF, I = IRQ disable,
F = FIRQ disable.

After this comes an operation:
00IxxxxSssssdddd222222222222 - ALU op d = s op 2
000000ASdddd3333ssss10012222 - Multiply d = s op 2 (+ 3 if A=1)
01IPUBWLssssdddd222222222222 - Load/store - d <-> [s +/- 2]
100PUSWLssssmmmmmmmmmmmmmmmm - multi-reg trasnfer (m = mask, s = base reg)
101Ldddddddddddddddddddddddd - branch (link to R14 if L=1).  PC += d*4.
110                          - coprocessor
1110                         - coprocessor
1111xxxxxxxxxxxxxxxxxxxxxxxx - SWI

On the ALU ops and multiply, the condition codes are set iff S=1.
The 12-bit src2 field and the I bit determine the second ALU input.
If I=1, src2 is an immediate value, of the form rrrriiiiiiii, and
the value is the zero-extended byte i rotated right 2*d bits.  Note
that the 8 ALU status bits fit into such a field.  If I=1, src2
is either ssssstt0rrrr, register r shifted (type t) by s bits
(tt = 00 for LSL, 01 for LSR, 10 for ASR, 11 for ROR), or
ssss0tt1rrrr, where ssss is the register holding the shift count.
(One extra cycle for this form.)

The ALU ops are xxx = 
0000 AND
0001 EOR
0010 SUB dest = src1 - src2
0011 RSB dest = src2 - src1
0100 ADD
0101 ADC
0110 SBC
0111 RSC (reverse sub with carry)
1000 TST as add, but dest unchanged
1001 TEQ as EOR, but dest unchanged
1010 CMP as SUB, but dest unchanged
1011 CMN as ADD, but dest unchanged
1100 ORR logical OR
1101 MOV dest = src2
1110 BIC dest = src1 & ~src2
1111 MVN dest = -src2

if dest=R15, if S=0, only the 24 PC bits are affected.  If S=1, all
32 bits are written (28 in user mode; mode bits and IRQ disables are
unwriteable).o

On the load/stores, the flag bits mean the following:
L - 1=load, 0=store
W - if 1, write result of address computation back to src1 register
B - 1=byte, 0=word
U - 1=ALU computes src1+src2, 0=ALU computes src1-src2
P - 1=src1 op src2 used as memory address; 0 = src1 used as memory address,
    and src1 op src2 only used for writeback (post-indexing).

On the multi-register load/stores, the bits mean the same thing, except that
they're repeated for each bit set in the mask, and the offset is always 4.
Multi-register transfer has an S bit, which controls loading the condition
codes.  If clear, only the PC is loaded (resulting in a jump).

Except for the lack of signed loads and halfword addressing, it's a
great chip.

Oh, yes, each of the 4 processor states (user,  supervisor, IRQ, FIRQ)
has its own copy of R14 (link register) and R13 (usually used as stack
pointer).  FIRQ also has its own R8, R9, R10, R11 and R12.  An interrupt
is a branch and link to a different state's R14.
-- 
	-Colin
