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From: bob@tera.com (Bob Alverson)
Subject: Re: Compilers and efficiency
Message-ID: <1991Apr29.160541.12800@tera.com>
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References: <4082@batman.moravian.EDU> <1991Apr28.154603.8003@rice.edu> <11489@mentor.cc.purdue.edu>
Date: Mon, 29 Apr 91 16:05:41 GMT

In article <11489@mentor.cc.purdue.edu> hrubin@pop.stat.purdue.edu (Herman Rubin) writes:
>[stuff deleted]
>The real2int conversion still has to be done on most machines, and also
>an integerize of real.  But suppose that the machine has integer hardware
>comparable to floating hardware, and can also handle unnormalized floats.
>Then one could put a shifted significand of f1 in a double register,
>divide by the significand of f2, setting iq to be the quotient, and 
>the remainder with the exponent of f2, and then normalized, as fr.
>Now I wonder how many of the readers would think of doing it this way?
>And how would the hardware designers recognize that putting the operation
>in hardware might be a good idea?
>

Gee, and what does the hardware do if the division is 1e300 / 1e-300?
It's got to extract about 2000 bits of quotient before it gets all the
integer bits.  I take it you really want

	iq = (f1 / f2) % some-power-of-two

Since continuable instructions don't mesh well with pipelined systems,
most hardware would only calculate 53 or maybe 64 quotient bits at a
time.  For example, look at the remainder *sequence* used on the 80x87.
Nobody wants to wait for the full calculation to finish before taking
an interrupt or context switching.

Strange as it may seem, the dividers in today's computers can compute
the correct quotient without having the correct remainder around to
return to the user.  Fortunately, some can compute the correct remainder
in one operation with a fused multiply add.
>-- 
>Herman Rubin, Dept. of Statistics, Purdue Univ., West Lafayette IN47907-1399
>Phone: (317)494-6054
>hrubin@l.cc.purdue.edu (Internet, bitnet)   {purdue,pur-ee}!l.cc!hrubin(UUCP)

Bob Alverson, Tera Computer
Resident arithmetic lunatic

