Newsgroups: comp.arch
Path: utzoo!utgpu!watserv1!watdragon!rose!ccplumb
From: ccplumb@rose.uwaterloo.ca (Colin Plumb)
Subject: Re: Vector processors, i860
Message-ID: <1991Feb3.224417.4106@watdragon.waterloo.edu>
Keywords: Vector, array processors, i860.
Sender: daemon@watdragon.waterloo.edu (Owner of Many System Processes)
Organization: University of Waterloo
References: <798@nvuxl.UUCP> <1991Feb3.061217.21988@watdragon.waterloo.edu> <1991Feb03.082253.12458@kithrup.COM>
Date: Sun, 3 Feb 91 22:44:17 GMT
Lines: 11

Oh, yes, excuse me for not remembering this in my first post... one of the
more amusing forbidden code sequences is jumping into a delay slot.
this is because there's no MIPS-like branch delay bit; you have to
examine the instruction at PC-4 (or PC-8 if in double-instruction mode)
to see if it's a taken branch.  This instruction, of course might be
on a differnt page, and it might not be paged in.  If you're sure it
wasn't paged in one (user) cycle ago, you can assume you just branched
to the faulting instruction and don't have to read the other page, but
are you completely sure of that?
-- 
	-Colin
