Newsgroups: comp.arch
Path: utzoo!henry
From: henry@zoo.toronto.edu (Henry Spencer)
Subject: Re: GC triggering and stack limit checking by MMU hardware
Message-ID: <1990Jul25.162446.28441@zoo.toronto.edu>
Organization: U of Toronto Zoology
References: <1990Jul19.151524.22544@diku.dk> <11075@alice.UUCP> <3729@auspex.auspex.com>
Date: Wed, 25 Jul 90 16:24:46 GMT

In article <3729@auspex.auspex.com> guy@auspex.auspex.com (Guy Harris) writes:
>I think most RISC machines (not entirely surprisingly) have less or no
>context of that sort; I'd expect things to work OK on a SPARC-based Sun,
>for example, as well as a MIPS-based machine. 
>
>In fact, what architectures other than the 68K architectures have lots
>of context for that?  I don't think the 386 or the WE32K, for example,
>have that problem.

I think it's really only an issue on the stack-puke machines, and I
think the 680[123]0 is the full list.  I seem to recall reading that
Motorola has gone for instruction retry rather than restart on the 68040,
which may mean that the stack puke is gone too.  It was always sort of
an artifact of Motorola CPUs not keeping enough information around to
back out of a faulting instruction.

(Well, I should qualify the above or Mike will jump on me... :-)  I
think the 680[123]0 is the full list until you start getting up into the
supercomputer range where the speed of light is a big problem.)
-- 
NFS:  all the nice semantics of MSDOS, | Henry Spencer at U of Toronto Zoology
and its performance and security too.  |  henry@zoo.toronto.edu   utzoo!henry
