Newsgroups: gradnews,ont.events
Path: utzoo!utgpu!jarvis.csri.toronto.edu!baldwin.csri!itrctor
From: itrctor@csri.toronto.edu (Ron Riesenbach)
Subject: ITRC Seminar: Sigma Delta A-to-D Converters for Telecom. Applications
Message-ID: <1989Jun13.173705.1961@jarvis.csri.toronto.edu>
Organization: University of Toronto, CSRI
Distribution: ont

     _S_i_g_m_a _D_e_l_t_a _A-_t_o-_D _C_o_n_v_e_r_t_e_r_s _f_o_r _T_e_l_e_c_o_m_m_u_n_i_c_a_t_i_o_n_s _A_p_p_l_i_c_a_t_i_o_n_s

  Lectures by two leading experts in Analog-to-Digital Converter Design.

          Hosted by Professors Andre Salama and Martin Snelgrove
                                     &
                               Presented by:
                  _I_n_f_o_r_m_a_t_i_o_n _T_e_c_h_n_o_l_o_g_y _R_e_s_e_a_r_c_h _C_e_n_t_r_e


Date:       Friday, July 7, 1989

Time:       10:00 - 12:00 noon

Location:   University of Toronto, Galbraith Bldg. Rm 248,  35  St.  George
            Street, Toronto.


                  _S_I_N_G_L_E _B_I_T _S_I_G_M_A _D_E_L_T_A _D_A_T_A _C_O_N_V_E_R_S_I_O_N
                     _J_e_f_f_r_e_y _W. _S_c_o_t_t, _A_T&_T _B_e_l_l _L_a_b_s


     Compared to classical data conversion techniques, single bit  oversam-
pled sigma delta architectures offer linearity performance that is indepen-
dent of component matching.  The shift in processing burden from the analog
to  digital domain that results from the speed/accuracy tradeoff makes CMOS
the technology of choice for sigma delta implementation.

     The principle of operation of single and double loop sigma delta  con-
verters will be presented, followed by a discussion of CMOS performance and
implementation issues such as noise/linearity limits, DSP complexity, limit
cycle oscillations and higher order loop instability.  Particular attention
will  be  given   to   production-oriented   concerns   focusing   on   the
design/manufacturing cycle time.

     The talk will conclude with a discussion of the  "extreme"  in  single
bit  architectures - the fourth order interpolative modulator recently pro-
posed by the Massachusetts Institute of Technology.


         _D_I_G_I_T_A_L_L_Y _C_O_R_R_E_C_T_E_D _M_U_L_T_I-_B_I_T _S_I_G_M_A _D_E_L_T_A _D_A_T_A _C_O_N_V_E_R_T_E_R_S
           _G_a_b_o_r _C. _T_e_m_e_s, _U_n_i_v_e_r_s_i_t_y _o_f _C_a_l_i_f_o_r_n_i_a, _L_o_s _A_n_g_e_l_e_s


      Sigma delta data converters using multi-bit internal A/D and D/A con-
verters  (noise-shaping  converters)  have lower quantization noise and are
more stable than  the  usual  single-bit  systems.  However,  the  required
linearity of the internal multi-bit DAC is very difficult to achieve for an
untrimmed integrated converter.  This paper describes several novel  multi-
bit  sigma  delta converters which use digital correction schemes to cancel
the errors due to the nonlinearity of the  internal  DAC.   Simulation  and
experimental  results  are given.  They verify the high accuracy achievable
with the proposed systems.
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This event is free to all industrial affiliates of  the  ITRC  as  well  as
faculty and students at the participating institutions.  Industrial affili-
ates are invited to join the speakers for lunch and  a  tour  of  the  VLSI
design  laboratories  after the talks.  Industrial affiliates are requested
to register for this event by phoning Rosanna Reid  at  (416)  978-8558  by
July 4th, 1989.
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