[HN Gopher] Visualizing CPU Pipelining (2024)
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       Visualizing CPU Pipelining (2024)
        
       Author : flipacholas
       Score  : 39 points
       Date   : 2026-04-13 18:26 UTC (4 hours ago)
        
 (HTM) web link (timmastny.com)
 (TXT) w3m dump (timmastny.com)
        
       | empiricus wrote:
       | Maybe it's just me, but the visualizations do not help me at all.
        
         | artemonster wrote:
         | I am always puzzled by such articles - its actually very well
         | made, drawings are good, little interactive pipeline animations
         | are fine. But in order to follow it you must already know and
         | understand what its writeen about and if you dont - the content
         | is just noise for you.
        
           | cogman10 wrote:
           | The article does say what it expects you to know before
           | reading. However, it has a dead link to the knowledge it
           | wants you to know.
        
       | inetknght wrote:
       | The best presentation I've seen about CPU performance related to
       | pipelining, branch prediction, and speculative execution was
       | Chandler Carruth's "Going Nowhere Faster" presentation at CppCon
       | 2017 [0]. I do recommend watching the _whole_ presentation, but
       | if you watch nothing else then just watch the 5 minutes or so
       | from the linked timestamp.
       | 
       | [0]: https://youtu.be/2EWejmkKlxs?t=2511
        
         | omcnoe wrote:
         | It also contains a wonderfully prescient question asked right
         | at the end of the talk: "... the processor gonna speculate,
         | doing some loads out of the bounds of the array, how does it
         | work in the hardware that it doesn't crash?"
         | 
         | Left unanswered at the time. I believe Spectre was known but
         | not publicly disclosed at this time.
        
       | risingedge wrote:
       | If anyone is interested, at https://sonic-rv.ics.jku.at/ we built
       | an educational platform for web-based simulation and
       | visualization of RISC-V processor architectures.
       | 
       | Our pipeline visualization is reconstructed from real RTL traces
       | (you can run your on programs which are simulated using GHDL).
       | 
       | Under examples you can find some different architectures based on
       | the Harris&Harris book on computer architecture.
        
       | jhallenworld wrote:
       | Now do a dynamic scheduling out of order engine with renaming, 20
       | pipes, speculative execution and hundreds of instructions in
       | flight. I guess you could make a multi-person game for this.
        
       | smallpipe wrote:
       | CPUs haven't worked like that in anything but a microcontroller
       | for half a century
        
         | alain94040 wrote:
         | Correct (well, maybe not half a century, maybe 30 years or so).
         | I was just about to reply that I'd love a version of this that
         | shows instructions going in and out of a re-order buffer. That
         | would be enlightening.
        
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       (page generated 2026-04-13 23:00 UTC)